IEEE - CAS Bangalore Chapter, India     CAS Chapter - Region 10
Institute of Electrical and Electronics Engineers - Circuits and Systems Society
Goals: To conduct seminars, workshops, and other events pertaining to all aspects of electronic circuits and systems

Events - 2005
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December
Seminar on On-chip Adaptive Components for Low-Power High-Performance Multimedia Processing
TACT, VSI, and IEEE CAS Society Bangalore Chapter jointly announce a
Technical Seminar
Speaker: Dr Rama Sangireddy (University of Texas, Dallas)
Date: December 28, 2005
Time: 10.30 AM - 11.30 AM
Venue: TI Bangalore Auditorium

Registration: Please RSVP to Arvind Chokhani who has been copied on this mail. The seminar is open to everyone, including contract employees. Please feel free to forward to your colleagues.

Abstract: Applications depending on their nature demand either higher computing capacity or larger data storage capacity or both. Hence, providing on-chip memory and computing resources that are fixed in nature is expensive and does not enable an efficient utilization of on-chip silicon real estate. To efficiently utilize silicon real-estate on the chip, we exploit the possibility of using a part of on-chip memory elements for computational purposes to strike a balance in the usage of memory and computing resources for various applications. In this research, we explore the possibility of converting a part of the data cache as a Reconfigurable Functional Cache (RFC), that can be configured to perform a selective core function in the media application whenever such computing capability is required. Such an architecture is shown to provide speedups ranging from 1.04x to 5.0x for various multimedia applications, with a considerable reduction in power consumption due to the reduced utilization of various other components on the chip. In this research, we also have designed the circuit of an Adaptive Register File Computing (ARC) unit, a novel on-chip dual-role circuit with a minimal area overhead of 0.233 sq.mm at 0.18 micron technology. It supplements the conventional register bank to provide larger register storage capacity, or acts as a specialized computing unit to provide higher on-chip computing capacity, depending on the requirement of a specific application. The talk will discuss the circuit level details for the implementation of the dual-role ARC unit, its integration in a processor pipeline, and the corresponding performance enhancement in various multimedia applications.

About the speaker: Rama Sangireddy is currently an Assistant Professor in the Department of Electrical Engineering at University of Texas at Dallas, USA, where he is also an affiliated faculty in the Computer Engineering program. He had earned his Ph.D. degree in Computer Engineering from Iowa State University, in August 2003, where he received Research Excellence Award in recognition of his outstanding research accomplishments. Earlier, he had obtained his M.S. degree in Electrical Engineering in May 1999 from University of Missouri-Rolla, USA, and his B.Tech degree with distinction in Electrical and Electronics Engineering in May 1996 from National Institute of Technology, Warangal, India. His research interests include, Computer Architecture, Adaptive computing systems, Fault-Tolerant systems design, and Computer Communications Networks. He is currently serving on technical program committee of various IEEE conferences, and he is a member of the IEEE.


Workshop on VLSI Physical Design Automation
December 19-21, 2005
Hotel Atria, Bangalore India
Organized by: VLSI Society of India
In cooperation with: IEEE Solid State Circuits Society and IEEE Circuits and Systems Society, Bangalore Chapter
Conducted by: Dinesh Bhatia (University of Texas at Dallas)

Registration: Download Information Flyer and Registration Form

Abstract: VLSI Design is experiencing tremendous growth due to advances in technology and scaling in feature sizes. As designers are given greater ability to pack more logic in a VLSI chip, the process of generating layouts is also becoming increasingly complex. CAD tools have to deliver effective solutions for vastly scaled up problems and in the presence of very stringent constraints. A designer must understand the problems associated with the design as well as the workings of CAD tools to arrive at early design closure.

This short course is primarily designed for introducing the physical design automation of VLSI systems. Thus, primary focus is on the algorithms for designing tools. However, each topic also deals with the complexity of design and thus provides opportunities for designers for preparing to tackle large complex designs. Design automation related issues for the current state of the art will set the theme and introduce problems in existing techniques in VLSI design. Data structures and algorithms related to design automation will provide insight into design of CAD tools.

The course will provide understanding and relationships between design automation algorithms and various constraints posed by VLSI fabrication and design technology. Critical performance related parameters and their importance in design automation tools would be introduced.

About the speaker: Dinesh Bhatia is member of faculty of electrical engineering at The University of Texas at Dallas. He is also program head for computer engineering at UT-D. He directs research activities within the Embedded and Adaptive Computing group and is also a member of Center for Integrated Circuits and Systems at the University of Texas at Dallas.

He received a Bachelor's in Electrical Engineering from Regional Engineering College, Suratkal, India, and a MS and a Ph.D. in Computer Science from the University of Texas at Dallas. His research interests include all aspects of reconfigurable and adaptive computing, architecture and CAD for field programmable gate arrays (FPGAs), physical design automation of VLSI Systems, power aware programmable architectures, network on chip solutions for SoCs and, computer engineering education.

He has extensive experience in building large scale embedded and reconfigurable systems. Some of these activities include principal designer and investigator for RACE and NEBULA systems for Wright Laboratories of USAF, principal investigator for DARPA funded REACT program, Co-PI on AFRL funded SPARCs program and several more. He has collaborated on phase 1 and phase 2 SBIR programs to build product prototypes.

He has published extensively in leading journals and conferences and continues to serve on program committees of several conferences. He is a senior member of IEEE, Computer Society, Circuits and Systems Society, Eta Kappa Nu, and recently served on the editorial board of IEEE Transactions on COMPUTERs.


Tutorial on Source Coding
Technical Seminar
TACT and IEEE Circuits and Systems Society Bangalore Chapter
Speaker: Ajit Rao (TI India)
Date: December 8, 2005
Time: 4.00 pm - 6.00 pm
Venue: TI Bangalore Auditorium

Registration: This talk is open to everyone. Please RSVP to Arvind Chokhani of TI (arvind_chokhani@ti.com)

Abstract: The tutorial aims to give you an insight into fundamental stunningly elegant theory behind Multimedia Codecs. In simple terms, the speaker will attempt to explain one of the most important thought- provoking contributions in information theory (Shannon's rate distortion bound capacity theorem) relate it to techniques used in real Codecs (scalar vector quantization, DCT FFT).


A Two-day Workshop on VLSI Signal Integrity
Date: December 16 - 17, 2005
Venue: Hotel Atria, Bangalore
Organized by VLSI Society of India
In cooperation with: IEEE Circuits and Systems Society, Bangalore Chapter
Speakers: Dr. Ram Achar (Carleton University, Canada); Dr. Ashok Balivada (Analog Devices, India); Dr. Shabbir Batterywala (Synopsys, India); Arvind (Texas Instruments India), and Dr. C.P. Ravikumar (Texas Instruments India).

Registration: Download Information Flyer and Registration Form

Abstract: As VLSI technology scaling continues, designers have to deal with problems of signal integrity. Capacitive cross-coupling between adjacent wires can lead to glitches and/or delay variations. Simultaneous switching of signals in the circuit can lead to power integrity problems. Precautions are necessary to ensure that signal integrity problems do not lead to failures during circuit operation. Over the past decase, EDA tools and design flows have evolved to deal with signal integrity problems. This workshop will deal with various aspects of signal integrity and provide both a tutorial overview as well as an industrial perspective of the problem.

About the speakers: Dr. Ram Achar obtained his M.E. from BITS, Pilani and Ph.D. from Carleton University, Canada. He is currently an Associate Professor at Carleton University. He has published a large number of papers in International Conferences and Journals. He is the author of six books, including "Introduction to High-Speed Circuit and Interconnect Analysis". He is the recipient of several best paper awards.

Arvind is Member, Group Technical Staff at Texas Instruments, India. He has led the development of in-house flows for crosstalk delay calculation at TI. His areas of interest include Signal Integrity, Physical Design, and Statistical Timing Analysis.

Dr. Ashok Balivada graduated from IIT-Bombay and did his Doctorate from the University of Texas at Austin. His area of interest is Design and Testing of VLSI systems. Currently he is Design Manager at Analog Devices, India.

Dr Shabbir Batterywala obtained his Ph.D. degree from IIT Bombay. He is currently part of the Advanced Research Group at Synopsys, India. His research interests are in the areas of Signal Integrity, Circuit Extraction, and Physical Design. He has published a large number of papers in international conferences and journals.

C.P. Ravikumar is with Texas Instruments India as a Senior Technologist in VLSI Test. Before joining TI, he served on the faculty of the Department of Electrical Engineering at IIT Delhi as a Professor. He has published over 200 papers in International conferences and journals. He is the recipient of best paper award (VLSI Design conference) and best student paper award (VLSI Design conference). He is a senior member of IEEE, Fellow of the Indian Microelectronics Society, and current secretary of VSI.


A Three-day Intensive Course on Design for Testability - Theory and Practice
A Three-day Intensive Course
Date: December 15 - 17, 2005
Venue: IIT New Delhi, India
Organized by VLSI Society of India
In cooperation with: IEEE Circuits and Systems Society
Instructors:
Dr.Vishwani D. Agrawal (Auburn University) and Dr.C.P. Ravikumar (Texas Instruments India)

Registration: Download Information Flyer and Registration Form

About the speakers: Dr. Vishwani D. Agrawal is James J. Danaher Professor of Electrical &Computer Engineering at Auburn University, Auburn, Alabama, USA. He has over thirty years of industry and university experience, working at Bell Labs, Rutgers University, TRW, IIT in Delhi, EG&G, and ATI. His areas of research include VLSI testing, low-power design, and microwave antennas. He has published over 250 papers, holds thirteen U.S. patents and has co-authored 5 books including Essentials of Electronic Testing for Digital, Memory and Mixed-Signal VLSI Circuits with Michael Bushnell at Rutgers. He is the founder and Editor-in-Chief of the Journal of Electronic Testing: Theory and Applications, was a past Editor-in-Chief of the IEEE Design & Test of Computers magazine, and is the Founder Editor of the Frontiers in Electronic Testing Book Series.

Dr. Agrawal is a co-founder of the International Conference on VLSI Design, and the International Workshops on VLSI Design and Test, held annually in India. He served on the Board of Governors of the IEEE Computer Society in 1989 and 1990,and, in 1994, chaired the Fellow Selection Committee of that Society. He has received seven Best Paper Awards, the Harry H. Goode Memorial Award of the IEEE Computer Society, and the Distinguished Alumnus Award of the University of Illinois at Urbana-Champaign. Dr. Agrawal is a Fellow of the IETE-India, a Fellow of the IEEE and a Fellow of the ACM. He has served on the advisory boards of the ECE Departments at University of Illinois, New Jersey Institute of Technology, and the City College of the City University of New York.

Dr. C.P. Ravikumar is with Texas Instruments India as a Senior Technologist in VLSI Test. Before joining TI, he served on the faculty of the Department of Electrical Engineering at IIT Delhi as a Professor. He has published over 150 papers in international conferences and journals. He has served as the technical program chair for VLSI Design Conference and the VLSI Design and Test Symposium. He has also served as the member of the program committee for several conferences, including HiPC. He is the recipient of SIGDA student scholarship award, best paper award (VLSI Design conference) and best student paper award (VLSI Design conference). He is a senior member of IEEE, Fellow of the Indian Microelectronics Society, and current secretary of VSI.


November
Technical Talk SYMMETRY AND ITS APPLICATIONS IN MULTIDIMENSIONAL SIGNAL PROCESSING
Sponsored by IEEE CAS Society, Bangalore and TACT, TI
Speaker: Prof. M.N.S. Swamy (Concordia University, Canada)
Date: November 30, 2005 (Wednesday)
Time: 4.00 pm – 5.30 pm
Venue: TI Bangalore Auditorium

Abstract: Symmetry is an important aspect of nature. It has been widely studied and used to simplify the analysis and design of physical systems as well as to add beauty and balance to them. This concept has been applied to abstract entities, as well as in the fields of quantum mechanics and crystallography. One-dimensional systems can only have a limited number of symmetries. Two- and higher dimensional systems may exhibit many types of symmetry. These may be used to advantage in reducing the complexity of design and implementation of such systems.

In this talk, we will be concerned with various types of symmetries that may be present in two- or three- dimensional filters. Since the frequency and impulse response functions of these filters are related, symmetry in one function induces certain of form of symmetry in the other. We will discuss these interdependencies and explore their applications. In particular, we will discuss the design of 2-D FIR and IIR filters by employing various types of symmetries in the frequency response of these filters. The usefulness of symmetry in reducing the complexity in 2-D FFT algorithm will also be considered. In addition, the question of stability of two- and higher dimensional systems, both with and without nonessential singularities of the second kind, will be examined.

About the speaker: M.N.S. Swamy received the B.Sc. (Hons.) degree in Mathematics from Mysore University, India, in 1954, the Diploma in Electrical Communication Engineering from the Indian Institute of Science, Bangalore in 1957, and the M.Sc. and Ph. D. degrees in Electrical Engineering from University of Saskatoon, Canada in 1960 and 1963 respectively.

He is presently a Research Professor and the Director of the Center for Signal Processing and Communications in the Department of Electrical and Computer Engineering at Concordia University, Montreal, Canada, where he served as the Chair of the Department of Electrical Engineering from 1970 to 1977, and Dean of Engineering and Computer Science from 1977 to 1993. Since July 2001, he holds the Concordia Chair (Tier I) in Signal Processing. He has also taught in the Electrical Engineering Department of the Technical University of Nova Scotia, Halifax, and the University of Calgary, Calgary, as well as in the Department of Mathematics at the University of Saskatchewan. He has published extensively in the areas of number theory, circuits, systems and signal processing, and holds four patents. He is the co-author of two book chapters and three books: Graphs, Networks and Algorithms (New York, Wiley, 1981), Graphs: Theory and Algorithms (New York, Wiley, 1992), and Switched Capacitor Filters: Theory, Analysis and Design (Prentice Hall International UK Ltd., 1995). He is the Editor-in-Chief of the journal Circuits, Systems and Signal Processing, for which he was an associate editor since its inception, and an Associate Editor of the Fibonacci Quarterly. He is a member and the Concordia University coordinator for Micronet, a National Network of Centers of Excellence in Canada.

Dr. Swamy is a Fellow of a number of professional societies including the Institute of Electrical and Electronic Engineers, the Institute of Electrical Engineers (UK), the Engineering Institute of Canada, the Institution of Engineers (India), and the Institution of Electronic and Telecommunication Engineers India). He is also a member of the Eta Kappa Nu, an Honor Society of Electrical Engineers. He has served the IEEE in various capacities such as the Vice President of the IEEE CAS society in 1976, Program Chair for the 1973 IEEE CAS Symposium, General Chair for the 1984 IEEE CAS Symposium, and the Vice-Chair for the 1999 IEEE CAS Symposium and a member of the Board of Governors. He was an Associate Editor of the Transactions on Circuits and Systems during 1985-87. He is a co-recipient of the IEEE CAS 1986 Guillemin-Cauer Best Paper Award.

He is the recipient of many awards including the Commemorative Medal for the 125th Anniversary of the Confederation of Canada issued in 1993 by the Governor General of Canada, in recognition of his significant contributions made to Canada and the community. In 1989, in honor of his many contributions, his past graduate students instituted at the Indian Institute of Science two awards in his name? M.N.S. Swamy Merit Scholarship, and M.N.S. Swamy Gold Medal. In 1987, he was awarded the Concordia University Guinea Pig award for the introduction of the innovative joint doctoral program between Concordia and the Southeast University in China. In 1993, Concordia University inaugurated the M.N.S. Swamy Computer Integrated Manufacturing laboratory "in appreciation of his sixteen years of support, dedication and leadership as Dean of the Faculty of Engineering and Computer Science". He is a co-recipient of the IEEE CAS 1986 Guillemin-Cauer Best Paper Award. In 2001, he received the IEEE-CAS Society Golden Jubilee Medal, as well as the year 2000 IEEE-CAS Society Education Award. In August 2001 he was awarded Doctor of Science in Engineering (Honoris Causa) by Ansted University "in recognition of his exemplary contributions to the research in Electrical and Computer Engineering and to Engineering Education, as well as his dedication to the promotion of Signal Processing and Communications Applications".


First Workshop on Design Verification Methodologies
Date: November 25, 2005
Venue: Hotel Atria, Bangalore, India
Organized by: VLSI Society of India
In cooperation with: Design Verification Forum - India, IEEE Circuits and Systems Society, Bangalore Chapter
Speakers:
Mahesha Puttanna, Wipro Technologies
Srinivasan Venkataramanan, Synopsys, India
Badri Gopalan, Ageia Technologies
Venkatesan Swaminathan, Intel, Bangalore
Vinaya Singh, Cadence Design Systems
Sundaresan Kumbakonam, Broadcom
Venkatesh Natarajan, Texas Instruments India.

Registration: Download Information Flyer and Registration Form

Workshop Goals: Design Verification is one of the most time-consuming of all the steps in the design flow. Many new methodologies are emerging to improve the cycle time of design verification. This workshop will provide an exposure to some of the recent developments in VLSI Design Verification.

About the speakers: Mahesha Puttanna is verification lead and a consultant at Wipro technologies with 8 years of experience in ASIC Verification. He has been instrumental in developing verification methodology for complex ASICs that has consistently delivered first silicon success. He developed test benches using languages like Verilog, VHDL, Vera and Specman. Mahesha earned his M. Tech from Sri Jayachamarajendra college of engineering, Mysore.

Srinivasan Venkataramanan is a senior Verification Solutions engineer with Synopsys Bangalore with extensive experience in pre-silicon verification. His primary interests are in constrained random, coverage driven, and assertion based verification. He has co-authored two books on assertion based verification and has published several papers in different forums. He holds a Masters degree in VLSI Design from IIT Delhi. He has work experience at Intel and Philips in the areas of RTL design and Pre-Silicon Verification.

Badri Gopalan has extensive experience working with HDLs and HVLs as a user, developer and architect. He currently works at Ageia Technologies. He has spent about 10 years at Synopsys, Riverstone Networks, and Cadence Design Systems. Badri has an MSEE from the University of Maryland, College Park and a B.Tech (EE) from IIT Bombay.

Vekatesan Swaminathan has several years of industry experience in design verification, test generators for pre silicon and post silicon environments. His interests are in validation environments for today's networking and processor platforms and building pre silicon environments, which can be reused for post silicon testing. He has published papers in various forums like IPSOC.

Sun Kumbakonam has over 16 years of experience in the field of Design Verification, working/consulting at HP, Phillips Semiconductors and Broadcom. He has verified complex SOC's in different domains with the help of environments using home brewed Verilog/C/PLI test benches and those using advanced features of Specman and VERA. He contributed as a reviewer of the book, Design Verification with E, by Samir Palnitkar. He leads the Network Switching Design Group for Broadcom India.

Venkatesh Natarajan has a B.E (Electronics) degree from University Visvesvaraya College of Engineering, Bangalore (1991). After spending a year with CMC Ltd, he has been with Texas Instruments since 1992. He started his career in TI in the memory modeling group and later moved to the C27x and C28x CPU architecture and verification team. His areas of expertise and current focus are CPU and debug architectures (CPU emulation) and hardware emulation and prototyping techniques for SoC.

Vinaya Singh is M.Tech in computer science from IIT Bombay and has over 10 years of experience in EDA product developments in the area of verification and synthesis. Vinaya is member of Accellera OVL committee and was task leader of IEEE VHDL synthesis standard 1076.6-2004. Vinaya holds two patents in the area of formal verification. Currently he is working as Senior Member of Consulting Staff at Cadence NOIDA R&D facility.

Harish Y.S. has an MS degree from BITS, Pilani, BE (Electronics & Comm)degree from BVBCET, Karnataka University (1998). His work experience includes 1 year at the Indian Institute of Science and six years with Texas Instruments, where he is involved in CPU design and verification. His area of focus is functional verification, methodologies for verification involving test generation, formal techniques and non-volatile memory testing.


September
Technical Talk on From ESL to Implementation: Chip Design in Half the Time Using Bluespec SystemVerilog
Sponsored by TACT, VSI and IEEE CAS Bangalore Chapter
Technical Talk
Speaker: Sathyam K. Pattanam (VP Engineering, Bluespec)
Date: Sep 8, 2005 (Thursday)
Time: 10.30 AM - 12.30 PM
Venue: TI Bangalore Auditorium

Registration: This talk is open to everyone!

Abstract: Bluespec develops high-level synthesis and simulation (above RTL) tools based on Bluespec SystemVerilog. Bluespec synthesis tool reads a design in Bluespec SystemVerilog and synthesizes it to Verilog RTL. The generated Verilog RTL goes through the rest of today's flow (simulation, synthesis, p&r, etc). Our approach is very unique from the earlier approaches to high-level synthesis. Our technology is based on TRS (Term Rewriting Systems) - a concept conceived at MIT by Prof. Arvind. Through concepts such as atomic behavior composition, protocol behavior expression, higher-level data abstraction and parameterization users can capture with Bluespec SystemVerilog designs at high-level of abstraction and still be able to achieve desired QoR (Qualify Of Results on the silicon). We have added specific constructs to SystemVerilog to introduce Bluespec concepts. Some of them have been already donated to the Accellera SystemVerilog v3.1a standard.

There are others we plan on donating once the committee opens up for donations. Through this approach we are seeing design and verification efforts reduced to at least half the time taken today. Please feel free to visit our web-site www.bluespec.com.


August
Seminar on Design For Testability - What is it and How did we get here?
TACT, VLSI Society of India, and IEEE CAS Bangalore Chapter announce a Seminar by
Speaker: T. W. Williams (Synopsys Fellow)
Date: Aug 16, 2005 (Tuesday)
Time: 11.00 AM – 12.00 Noon, Tea at 10.45 AM
Venue: TI Bangalore Auditorium

Abstract: Design has never been simple; it has been evolving since the 1970’s when it was considered very novel and radical! Today it is required by virtually all designs. This presentation will give a brief view of the motivation of testing that initially drove the Design For Testability, DFT era. The drive to achieve better quality, higher test coverage of the single Stuck at Fault model played a key role in the development of DFT techniques. This presentation will follow the growth of the LSSD to Built In Self Test, BIST. Out of the BIST era came the concept of seeds, which can be used to apply deterministic test to BIST like structure. A new DFT technique will be presented namely Adaptive Scan, which has very low overhead and does not utilize Linear Feedback Shift Registers, LFSRs. Due to the effects of scaling, defect mechanisms are no longer easily identified with single "stuck at" fault models but rather are demanding far more complex and challenging solutions. For example, shorts are now being extracted from the physical layout of a design, with special tests being created to detect them. But this is just the beginning; delay testing of all transition faults is now a new objective of DFT. Manufacturing and test are beginning to develop an even stronger relationship due to the close interconnection between yield ramp-up and diagnostics, which are supported by DFT structures included in the design.

In this presentation, T. W. Williams addresses these current challenges in the area of design for testability and diagnostics. In addition, he will discuss the future challenges facing designers, and the new tools and methodologies, which the design community will be dealing with.

About the speaker: Thomas W. Williams is a Synopsys Fellow at Synopsys. Prior to that Dr. Williams was with IBM Microelectronics Division in Boulder, Colorado, as manager of the VLSI Design For Testability group, which dealt with design for testability of IBM products. He received a BSEE from Clarkson University , an MA in pure mathematics from the State University of New York at Binghamton , and a Ph.D. in electrical engineering from Colorado State University.

Dr. Williams is engaged in numerous professional activities. He was the founder and chair of the annual IEEE Computer Society Workshop on Design for Testability. He was the co-founder of the European Workshop on Design for Testability. He is also the chair of the IEEE Technical Subcommittee on Design for Testability. He has been a program committee member of many conferences in the area of testing, as well as being a keynote or invited speaker at a number of conferences, both in the U.S. and abroad. He was selected as a Distinguished Visiting Speaker by the IEEE Computer Society from 1982 to 1985. He has been a special-issue editor in the area of design for testability for both the IEEE Transactions on Computers and the IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems. He has written four book chapters and over 100 technical papers on testing, edited a book and recently co-authored another book entitled Structured Logic Testing. (with E. B. Eichelberger, E. Lindbloom , and J. A. Waicukauski).

Dr. Williams has received a number of best paper awards, including the 1987 Outstanding Paper Award from the IEEE International Test Conference for his work in the area of VLSI Self-Testing, (with W. Daehn, M. Gruetzner, and C. W. Starke), a 1987 Outstanding Paper Award from the CompEuro'87 for his work on Self-Test, a 1989 Outstanding Paper Award (Honorable Mention) from the IEEE International Test Conference for his work on AC Test Quality (with U. Park and M. R. Mercer), and a 1991 Outstanding Paper Award from the ACM/IEEE Design Automation Conference for his work in the area of Synthesis and Testing (with B. Underwood and M. R. Mercer).

He is an Adjunct Professor at the University of Colorado, Boulder, and in 1985 and 1997 he was a Guest Professor and Robert Bosch Fellow at the Universitaet of Hannover, Hannover Germany. Dr. Williams was named an IEEE Fellow in 1988, "for leadership and contributions to the area of design for testability."

In 1989, Dr. Williams and Dr. E. B. Eichelberger shared the IEEE Computer Society W. Wallace McDowell Award for Outstanding Contribution to the Computer Art, and was cited "for developing the level-sensitive scan technique of testing solid-state logic circuits and for leading, defining, and promoting design for testability concepts." Some Previous Recipients of the W. Wallace McDowell Award - John W. Backus - FORTRAN, Seymour Cray - Super Computing, Gene Amdahl - Amdahl Computer, Grace Murray Hopper - Fundamental Technical Leadership, Gordon E. More - Semi-Conductor Development, C. Gordon Bell - Technical Design. He is a member of the, Eta Kappa Nu, Tau Bata Pi, IEEE, ACM, Sigma Xi, and Phi Kappa Phi. Dr. Williams, research interests are in design for testability (scan design and self-test), test generation, fault simulation, synthesis and fault-tolerant computing.


VDAT2005: 9th IEEE VLSI Design & Test Symposium
Date: August 10-13, 2005
Venue: Wipro Technologies, Electronics City, Bangalore, India
Organized by: VLSI Society of India
Industry Sponsors: TI India, Wipro Technologies and Intel India
In Cooperation With: IEEE EDS/SSCS, IEEE CAS Bangalore Chapter and IEEE-CS-TTTC

Information: Download Information Flyer ... Technical program
View Technical program online

Day 1 : August 10, 2005 - Wednesday (Tutorials)
Day 2 : August 11, 2005 - Thursday (VLSI Education Day)
Day 3 : August 12, 2005 - Friday
Day 4 : August 13, 2005 - Saturday


July
4-day Intensive Course on Design for Testability – Theory and Practice
Date: July 27-30, 2005
Venue: Hotel Atria, Bangalore, India
Organized by: VLSI Society of India
Corporate Sponsor: Tessolve, India
In co-operation with: IEEE Circuits and Systems Society, Bangalore Chapter and IEEE-CS-Test Technology Technical Council (TTTC)
Instructors:
Dr.Vishwani D.Agrawal and Prof.Adit D.Singh (Auburn University)

Registration: Download Information Flyer. If you need softcopy or hardcopy of the registration form, write to vsisecy@vlsi_india.tripod.com. Course fee includes registration material, lunch and refreshments on all the days. Transport and stay arrangements are the responsibility of the participants. Processing fee of Rs 1000/ - will be charged against cancellations.

Course content:

  • The exponential nature of the testing problem
  • Fault models
  • Stuck-at faults
  • Test generation for combinational circuits
  • D algorithm
  • PODEM, FAN and learning based ATPG
  • Fault coverage
  • Fault simulation
  • Fault grading
  • Testability measures
  • Test generation algorithms for sequential circuits
  • Scan and partial scan design
  • Functional testing of microprocessor/controllers
  • Design for testability
  • Built in self-test (BIST)
  • Test compression techniques for test data volume reduction
  • Boundary scan and the IEEE 1149 testability standard
  • Memory testing
  • Memory BIST
  • SOC test issues
  • P1500 core test standard
  • Current testing: IDDQ and IDDT
  • Structural delay testing
  • Fmax and MinVDD testing
  • Test cost and effective ness
  • Test coverage and defect levels
  • Stress testing
  • Reliability Screens for burn -in minimization
  • About the speakers: Adit D. Singh is James B. Davis Professor of Electrical & Computer Engineering at Auburn University, where he directs the VLSI Design & Test Laboratory. Earlier he has held faculty positions at the University of Massachusetts in Amherst, and Virginia Tech in Blacksburg. His research interests are in VLSI design, test, and reliability, and he has published extensively in these areas. Over the years he has taught approximately 50 short courses in-house for companies including IBM, National Semiconductor, TI, AMD, Bell Labs and Sandia Labs (earlier also for Digital, Control Data, and Data General), and at IEEE technical meetings, and through university extension programs. These have primarily been in the areas of VLSI design, test, reliability and fault tolerance. Prof. Singh currently serves on the Executive Committee of the IEEE Test Technology Technical Council, on the Editorial Board of IEEE Design and Test, and is the General Chair of the 2003 IEEE Memory Test Workshop. He is a Fellow of IEEE and a Golden Core Member of the IEEE Computer Society.

    Vishwani D. Agrawal is James J. Danaher Professor of Electrical & Computer Engineering at Auburn University, Auburn, Alabama, USA. He has over thirty years of industry and university experience, working at Bell Labs, Rutgers University, TRW, IIT in Delhi, EG&G, and ATI. His areas of research include VLSI testing, low-power design, and microwave antennas. He has published over 250 papers, holds thirteen U.S. patents and has co-authored 5 books including Essentials of Electronic Testing for Digital, Memory and Mixed-Signal VLSI Circuits with Michael Bushnell at Rutgers. He is the founder and Editor-in-Chief of the Journal of Electronic Testing: Theory and Applications, was a past Editor-in-Chief of the IEEE Design & Test of Computers magazine, and is the Founder and Consulting Editor of the Frontiers in Electronic Testing Book Series. Dr. Agrawal is a co-founder of the International Conference on VLSI Design, and the International Workshops on VLSI Design and Test, held annually in India. He served on the Board of Governors of the IEEE Computer Society in 1989 and 1990, and, in 1994, chaired the Fellow Selection Committee of that Society. He has received seven Best Paper Awards, the Harry H. Goode Memorial Award of the IEEE Computer Society, and the Distinguished Alumnus Award of the University of Illinois at Urbana-Champaign. Dr. Agrawal is a Fellow of the IETE-India, a Fellow of the IEEE and a Fellow of the ACM. He has served on the advisory boards of the ECE Departments at University of Illinois, New Jersey Institute of Technology, and the City College of the City University of New York.


    Seminar on Recent Advances in Coding Theory
    IEEE CAS Bangalore Chapter and TACT present a Seminar by
    Speaker: Krishna R. Narayanan, Associate Professor
    (Dept. of Elec Engg, Texas A&M University, College Station)
    Date: 25 July 2005 (Monday)
    Time: 4.00 – 5.00 PM
    Venue: TI Bangalore Auditorium

    Registration: This talk is open to everyone. Please RSVP to Arvind Chokhani - arvind_chokhani@ti.com

    About the event: Prof. Krihna Narayanan is a well known expert in the area of coding theory. His research interests are in Modulation and coding (Turbo codes, Low density parity check codes) for wireless communications Iterative Processing - Iterative equalization, demodulation etc Equalization and coding for Magnetic recording and wireless communications Joint source-channel coding Hardware implementation of LDPC decoders Prof. Narayanan will provide an overview of the recent advances in coding theory in this talk.


    VEDAS 2005: 2nd VLSI Embedded Systems DSP Applications Seminar
    VEDAS 2005
    Date: July 1-2, 2005
    Venue: Sona College of Technology, Salem, Tamilnadu, India
    Sponsored by: VLSI Society of India, Cadence, Analog Devices, Texas Instruments India
    Organized by: PSG College of Technology, Coimbatore
    In Co-operation with: IEEE Circuits and Systems Society, Bangalore, and IEEE Student Chapter, SCT and TTTC
    Speakers:
    V Kamakoti, IIT Madras
    Srinivasan Venkataraman, Synopsys
    N.J.R. Muniraj, Sona College of Technology
    Navkanta Bhat, IISc,Bangalore
    C. P. Ravi Kumar, Texas Instruments
    Rahul Kumar, National Semiconductors
    Vishal Dalal, Sasken
    Soujana Sarkar, Texas Instruments
    V. Ranganathan, Sathyam, Chennai
    Chandravel Sankarakumar, Sanmina, Bangalore

    Registration: Download Information Flyer and Registration Form

    Abstract: For further information, please log-on to: www.vedas2005.com. Queries must be sent directly to: queries@vedas2005.com


    June
    Custom LSI Design Workshop
    Venue: Manipal, Karnataka
    Date: June 6-18, 2005
    Sponsored by: VLSI Society of India and KarMic (Karnataka Micro Electronics, Manipal, Karnataka)
    In cooperation with: IEEE Circuits and Systems Society, Bangalore Chapter

    Registration: A uniform, non-refundable registration fee of Rs. 6000/- will be charged to participants. A discount of Rs 1000/- will be applicable to members of VSI – quote your VSI membership number. The fee includes simple accommodation, meals, and participation in the workshop with unlimited lab time. Travel and other expenses must be borne by the participant. A maximum of 30 participants will be admitted. Please send an application along with a Demand Draft payable to "VLSI Society of India" to be redeemable at Bangalore, India.

    Download Information Flyer and Registration Form

    Abstract: The workshop is intensive in hands-on activity and prior exposure to use of Linux/UNIX operating system is assumed. Certificates will be provided to participants from the VLSI Society of India upon successful completion of projects.

    The workshop is open to students and faculty with strong interest in VLSI. Preference will give given to students who have completed third year B.E./B.Tech or 1st year M.E/M.Tech. We encourage small groups of students and faculty from the same organization to apply to take full advantage of the workshop. The number of participants from a single organization will be limited by the committee. It is expected that the participant is familiar with basics of electronics, MOS transistor operation, and has done some reading in MOS LSI. The workshop has the following components:

  • Opportunity to participate in project definition and specification
  • Participate in design planning
  • Custom design of components and integration
  • Verification of the design
  • Performance analysis and improvement challenges
  • Participation in brainstorming sessions, group discussions
  • Listening to experts on VLSI Design and Test issues
  • Honing your team working skills

  • At the end of the workshop, the participant is expected to complete a design project, including its conceptualization, design, simulation, and custom layout implementation. There is a plan to fabricate successful projects from this effort through MOSIS. Participants of selected projects will be given an opportunity at the VDAT Symposium (www.vlsi_india.tripod.com) to present their work. In addition to custom LSI design experience, the participants will participate in group discussions and other team activities.

    About the event: The workshop will be conducted at the premises of KARMIC in Manipal, Karnataka. Manipal is close to both Mangalore and Udupi, both of which have good rail and road connections to all parts of India. Located in coastal Karnataka, Manipal offers excellent tourist opportunities for participants at the conclusion of the workshop.

    Workshop Steering Committee:
    Dr Shivaling Mahant-Shetti, KarMic
    Dr C.P. Ravikumar, TI, Bangalore
    Dr Navakanta Bhat, IISc, Bangalore
    Dr S. Karthik, Analog Devices
    Prof S.Kambalimath, BEC, Bagalkot
    Prof K.Srikant, BLDEA, Bijapur
    Prof B L Desai, BVBCET, Hubli
    Dr Narasimha Bhat, Manipal.net, Manipal
    Prof V Thomas, MIT, Manipal
    Mr Harishchandra Hebbar, MCIS,Manipal
    Prof N.Chiplunkar, NMAMIT, Nitte
    Dr Subbanna Bhat, NITK, Surathkal

    Organizing Committee:
    Kavita Itnal, Karmic (kavitai@karmic.co.in)
    Amit Patil, Karmic (amithp@karmic.co.in)
    Shruti Sampagavi, Karmic (shrutis@karmic.co.in)
    Vasudevan, Karmic (vasudevanp@karmic.co.in)
    Tasneem Mahant Shetti, Karmic (tasneem@karmic.co.in)


    May
    Seminar on The Future of Analog ICs
    Sponsors: TACT, VLSI Society of India, and The IEEE Circuits and Systems Society, Bangalore Chapter
    The seminar will present an expert's views on the future of Analog ICs
    Speaker: Prof. T.R. Viswanathan (UT Dallas)
    Date: May 19, 2005 (Thursday)
    Time: 5.00 PM – 6.00 PM
    Venue: TI Bangalore Auditorium

    Registration: The event is open to everyone. Please RSVP to ravikumar@ti.com

    Abstract: The seminar will present an expert's views on the future of Analog ICs.

    About the speaker: T. R. Viswanathan is a Research Professor at UT Dallas. He is a Fellow of IEEE, recipient of the CAS Darlington award, Jack Kilby award for the outstanding student paper of the year (2000) and the IEEE Third Millennium Medal. His teaching and research interests are in the broad area of Analog and Digital Integrated-Circuit Design for signal-processing applications. The key objectives are to reduce chip-area, cost, power (or energy) for enabling increased levels of integration in emerging technologies. His other interest is in starting profitable fab-less semi-conductor companies for creating challenging jobs and products that will improve the quality of life on this planet.


    April
    Technical talk on Introduction to Sigma Delta Converters
    Technical talk and Chapter meeting
    Sponsored by: IEEE Circuits and Systems Society, Bangalore Chapter
    Speaker: Dr. P.V. Ananda Mohan (ECIL)
    Date: April 26, 2005
    Time: 5.00 PM – 6.00 PM
    Venue: TI Bangalore Auditorium

    Registration: The talk is open to everyone. Please RSVP to Arvind Chokhani - arvind_chokhani@ti.com

    Abstract: Sigma delta converters are very important building blocks in state- of-the-art Mixed Signal ICs. Also known as over-sampled A/D converters, Sigma-delta converters help to reduce the analog part to bare minimum, thereby simplifying the Converter design. These use large sampling frequency thereby simplifying the anti-aliasing filter design. Several architectures have been described in the past two decades such as two-loop, Multistage noise shaping (triple integration based), Multi-loop feedback etc. Early designs were Low-pass structures whereas more recently band-pass sigma delta converters have been proposed and implemented.

    The early designs were for Analog to digital conversion but more recently, even digital to analog converters have been impemented using Sigma-delta principle. Applications in designing frequency synthesizers are aso available. In this introductory lecture, basic concepts of Sigma delta converters, Switched-capcitor implementations, the various non-idealities that need to be taken care of and also custom digital filter design to shape the noise spectrum are covered.

    About the speaker: Dr. P.V. Ananda Mohan (SM 1984 F 2005) obtained his Ph.D degree in Electrical Communication Engineering from Indian Institute of Science, Bangalore in 1975. Since 1973, he was with I.T.I. Limited in R&D till December 2003. Since January 2004, he was with Electronics Corporation of India Limited, Bangalore as Advisor (Telecom) and in November 2004, he was appointed Executive Director (Technical). His research interests are in the area of Analog VLSI design, VLSI architectures, Cryptography. He has published in these areas in refereed international journals and conferences. His book Switched Capacitor Filters: Theory, Analysis and Design coauthored with Dr. M. N. S. Swamy and Dr. V. Ramachandran was published by Prentice-Hall (London) in 1995. He has authored two more books Residue Number Systems: Algorithms and Architectures published in 2002 by Kluwer Academic Publishers and Current-mode VLSI analog Filters: Design and applications in 2003 by Birkhauser.

    He is a Fellow of IETE. He is the chair of IEEE CAS Chapter, Bangalore. He was the Associate Editor of IEEE Transactions on Circuits and Systems Part I during 2000-2003. He is an Honorary Editor of IETE Technical Review. He taught Mixed Signal Design for few semesters at the Indian Institute of Science, Bangalore. He has received the Ram Lal Wadhwa Gold Medal Award from the Institution of Electronics and communication engineers (India) in 2003 and Indira Priyadarshini Award in 2004.


    February
    Workshop on Low Power Design Techniques
    Date: February 25-26, 2005
    Venue: Golden Jubilee Hall, ECE Dept, IISc - Bangalore
    Sponsor: VLSI Society of India
    In cooperation with: IEEE Circuits and Systems Society (Bangalore Chapter), and IEEE Electron Devices and Solid State Circuits Society
    Speakers: Prof. Eric A. VITTOZ, Prof. Christian Piguet, Dr. Kiyoo ITOH, V. Ramgopal Rao, Dr C. Srinivasan

    Registration: Download Information Flyer and Registration Form

    About the speakers: Prof. Eric A. VITTOZ is an IEEE Fellow and has published more than 100 papers and holds 25 patents.He has been with the Centre Electronique Horloger S.A. (CEH), Neuchâtel, where he participated in the development of the first prototypes of electronic watches. He was the Vice-Director of CEH, supervising advanced developments in electronic watches and other micropower systems. Later, he took the responsibility of the Circuits and Systems Research Division of the Swiss Center for Electronics and Microtechnology (CSEM) in Neucâtel, where he was appointed Executive Vice-President, Integrated Circuits and Systems. He is also directly responsible for the Advanced Research section of CSEM. His field of personal research interest and activity is the design of low-power analog CMOS circuits, with emphasis on their application to advanced perceptive processing. Since 1975, he has been lecturing and supervising undergraduate and graduate student projects in analog circuit design at EPFL, where he became Professor in 1982.

    Prof. Christian Piguet joined the Centre Electronique Horloger S.A., Neuchâtel, Switzerland, in 1974. He worked on CMOS digital integrated circuits for the watch industry, low-power embedded microprocessors and CAD tools based on a gate matrix approach. Prof. Piguet is now Head of the Ultra-Low-Power Sector at the CSEM (Centre Suisse d'Electronique et de Microtechnique S.A), Neuchâtel, Switzerland. He is presently involved in design and management of low power and high speed integrated circuits in CMOS technology. His main interests include design of very low-power microprocessors, low-power standard cell libraries, gated clock and low-power techniques as well as asynchronous design. He is Professor at the Ecole Polytechnique Fédérale Lausanne (EPFL), Switzerland, he also lectures in VLSI and microprocessor design at the University of Neuchâtel, Switzerland, as well as other postgraduate courses in low-power design.

    Dr. Kiyoo ITOH has been leading RAM technology at Hitachi Ltd: He was the lead designer of the first prototype for eight generations of Hitachi DRAMs ranging from 4Kb to 64Mb. He initiated circuit inventions and developments to reduce sub-threshold current of MOSFETs even for the active mode, which is highlighted today in low-voltage CMOS LSI design. Typical examples of the reduction circuits are the dynamic substrate back-bias control, multi-threshold (Vt) CMOS logic, various gate-source (self) back-biasing schemes, and power switch that we take for granted today. He holds over 370 patents in Japan and US. He authored three books and one book chapter on memory designs, and contributed over 130 technical papers and presentations, many of them invited, in IEEE journals and conference proceedings. Dr. Itoh has won 16 honors in US, Europe, and Japan. They include the IEEE Paul Rappaport Award in1984, the Best Paper Award of ESSCIRC90, and the 1993 IEEE Solid-State Circuits Award. He is an IEEE Fellow. In Japan, his awards include the National Invention Award (Prize of the Patent Attorney's Association of Japan) in 1989, the Commendation by the Minister of State for Science and Technology (Person of Scientific and Technological Merits) in 1997, and the National Medal of Honor with Purple Ribbon in 2000.

    V. Ramgopal Rao is an Associate Professor in the Department of Electrical Engineering, IIT Bombay. He has over 140 publications in these areas in refereed international journals and conference proceedings and holds two patents. Prof. Rao is an Editor for the IEEE Transactions on Electron Devices in the CMOS Devices and Technology area and is a Distinguished Lecturer (DL), IEEE Electron Devices Society. He is a Senior Member, IEEE and a Fellow, IETE. Dr. Rao received the Swarnajayanti Fellowship award for 2003-2004, instituted by the Department of Science and Technology, Govt. of India. He is also a working group member setup by the Govt. of India on Nanotechnology. Prof. Rao was the organizing committee chair for the 17th International Conference on VLSI Design, and was Chairman, IEEE AP/ED Bombay Chapter during 2002-2003.

    Dr C. Srinivasan has been leading mixed signal and analog design projects at Texas Instruments, India for several years. He is currently working on aspects of power management in system-on-chip designs.

     

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