IEEE - CAS Bangalore Chapter, India     CAS Chapter - Region 10
Institute of Electrical and Electronics Engineers - Circuits and Systems Society
Goals: To conduct seminars, workshops, and other events pertaining to all aspects of electronic circuits and systems

Events - 2006
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First International Workshop on Interconnect Design and Variability
Date: December 28-29, 2006
Venue: Golden Jubilee Hall, ECE Dept, IISc, Bangalore, India
Organized by: VLSI Society of India
In cooperation with: Indian Institute of Science, Bangalore and IEEE Circuits and Systems Society, Bangalore Chapter

Registration: Refer Workshop announcement with registration Tariff

Scope of the Workshop: Interconnect scaling and variability are two difficult challenges in sub-100nm technology nodes. This workshop aims at addressing the following topics.

1. Latest advances in interconnect modeling and design innovations to continue performance scaling in sub-100nm technologies:
Technology scaling trends
New process realities in sub-100nm technologies
Alternative interconnect methods
Interconnect analysis algorithms
Design and Architecture methods to mitigate RC scaling

2. In depth review of the latest advances in variability in sub-100nm technologies:
Device and interconnect process variations
Algorithms related to statistical analysis of performance and leakage
Practical approaches to address variability
Variation tolerant design methods

General Co-Chairs:
Nagaraj, N.S. Texas Instruments (Dallas)
C.P. Ravikumar, Texas Instruments (Bangalore)

Program Committee:
Andrzej Strojwas, Carnegie Mellon University, USA
Dipu Pramanik, Synopsys, USA
Jaijeet Roychowdhury, Univ. of Minnesota, USA
Krishna Saraswat, Stanford University, USA
Larry Pileggi, Carenegie Mellon University, USA
Nickhil Jakatdar, Cadence Design Systems, USA
Poras Balsara, Univ. of Texas at Dallas, USA
Ram Achar, Carleton University, Canada
Sachin Sapatnekar, Univ. of Minnesota, USA
Yervant Zorian, Virage Logic, USA

Dr. Jaijeet Roychowdhury, University of Minnesota, USA
Dr. Krishna Saraswat, Stanford University, USA
Dr. Ram Achar, Carleton University, Canada
Dr. Shankar Balachandran, IIT Madras, Chennai, India
Vijay Sindagi, Texas Instruments, India
Dr. Tejas Jhaveri, Carnegie Mellon University, USA
Dr. Dipu Pramanik, Synopsys, USA
Dr. Mustafa Celik, Extreme DA, USA
Dr. Sarma Vrudhula, Arizona State Univeristy, USA
Dr. Vivek De, Intel, USA
Dr. N.S.Nagaraj, TI, Dallas

Seminar on Cooperative Communication where Network meets the Channel
PragaTI (TI India University) announces a seminar
In Cooperation with VLSI Society of India and IEEE Circuits and Systems Society Bangalore Chapter
Speaker: Behnaam Aazhang
(Dept of Elect and Comp Engg, Center for Multimedia Communication, Rice University, Houston, TX USA)
Date: October 3, 2006
Time: 10.00 AM – 11.00 AM
Venue: TI Bangalore Auditorium

Registration: The talk is open to everyone. If you are not an employee of TI, you must RSVP to before Sep 20 and arrive at least 15 minutes prior to the start of the seminar. There is limited seating.

Abstract: Within the last ten years, there has been a cultural shift from wired landlocked connectivity to pervasive wireless information access. Most mobile devices are now equipped with some form of embedded wireless radio. The market demands for high data rates and increased battery longevity have put tremendous pressure on all aspects of wireless system design. To meet the challenges of next generation wireless system, we need fundamentally new methods to exploit all available dimensions of communication channels as well as network.

Over the last few years, our research group at Rice has focused on emerging systems and network level techniques to increase spectral and power efficiency of communication systems, and extend coverage of wireless networks. The cooperative communication paradigm pools distributed resources of different nodes, such that the nodes act like a collaborative system instead of greedy adversarial participants. In this talk, I will first introduce Rice's Electrical and Computer Engineering Department, and then will talk briefly about various research activities in the Center for Multimedia Communication, and finally I will present the cooperative communication methodology and discuss its merits and challenges. The approach will be information theoretic and will consider coding, channel state information, and feedback. I will conclude by presenting our research and development plans to demonstrate feasibility of cooperation in the context of a scalable experimental wireless system for mobile broadband Internet.

About the speaker: Behnaam Aazhang received his B.S. (with highest honors), M.S., and Ph.D. degrees in Electrical and Computer Engineering from University of Illinois at Urbana-Champaign in 1981, 1983, and 1986, respectively.

From 1981 to 1985, he was a Research Assistant in the Coordinated Science Laboratory, University of Illinois . In August 1985, he joined the faculty of Rice University, Houston, Texas, where he is now the J.S. Abercrombie Professor, and Chair of the Department of Electrical and Computer Engineering. He has served as the founding director of Rice's Center for Multimedia Communications from 1998 till 2006. He has been a Visiting Professor at IBM Federal Systems Company, Houston, Texas, the Laboratory for Communication Technology at Swiss Federal Institute of Technology (ETH), Zurich, Switzerland, the Telecommunications Laboratory at University of Oulu, Oulu, Finland, the U.S. Air Force Phillips Laboratory, Albuquerque, New Mexico, and at Nokia Mobile Phones in Irving, Texas . His research interests are in the areas of communication theory, information theory, and their applications with emphasis on multiple access communications, cellular mobile radio communications, and wireless communication networks.

Dr. Aazhang is a Fellow of IEEE, a recipient of the Alcoa Foundation Award 1993, the NSF Engineering Initiation Award 1987-1989, and the IBM Graduate Fellowship 1984-1985, and is a member of Tau Beta Pi and Eta Kappa Nu. He is a distinguished lecturer of IEEE Communication Society and also a recipient of 2004 IEEE Communication Society's Stephen O. Rice best paper award for a paper with A. Sendonaris and E. Erkip. Dr. Aazhang has been listed in the Thomson-ISI Highly Cited Researchers and has been keynote and plenary speaker of several conferences. He is serving as a guest editor for IEEE Journal on Selected Areas of Communication special issue on relay and cooperative communication and the general chair of the 2006 Communication Theory Workshop, Dorado, Puerto Rico.

He has served on Houston Mayor's Commission on Cellular Towers 1998-2004, as the Editor for Spread Spectrum Networks of IEEE Transactions on Communications 1993-1998, the Treasurer of IEEE Information Theory Society 1995-1998, the Secretary of the Information Theory Society 1990-1993, the Publications Chairman of the 1993 IEEE International Symposium on Information Theory, San Antonio, Texas, the co-chair of the Technical Program Committee of 2001 Multi-Dimensional and Mobile Communication (MDMC) Conference in Pori, Finland, the chair of the Technical Program Committee for 2005 Asilomar Conference, Monterey, CA, and the co-chair of the Technical Program Committee of International Workshop on Convergent Technologies (IWCT), Oulu, Finland, June 6-10, 2005.

Seminar on Reducing time-to-volume: Diagnosis by Design Engineer
PragaTI, VLSI Society of India and IEEE Circuits and Systems Society (Bangalore Chapter) announce a seminar
In Cooperation with VLSI Society of India and IEEE Circuits and Systems Society Bangalore Chapter
Speaker: Dr. Rochit Rajsuman (Advantest America Corporation)
Date: September 29, 2006
Time: 2.00 PM - 3.00 PM
Venue: TI Bangalore Auditorium

Registration: This seminar is open to everyone.

About the speaker: Dr. Rochit Rajsuman received his Ph.D. in Electrical Engineering from CSU in 1988. He served on the faculty in the Department of Computer Engineering and Science at Case Western Reserve University for seven years. During that time, he also held a secondary appointment in the Department of Electrical Engineering. He left academia to join LSI Logic as Product Manager for Test Methodologies. Dr. Rajsuman then joined a media processor start-up, Equator Technologies. In 1998 he joined Advantest America R&D Center as Manager of Test Research. In 2001 he became Chief Scientist at Advantest America R&D Center and since 2004 is the Chief Scientist at Advantest America Corporation (the parent corporation).

He has authored/co-authored over 50 patents and numerous papers, and authored three books "System-on-a-Chip: Design and Test" in 2000, "Iddq Testing for CMOS VLSI" in 1995, and "Digital Hardware Testing" in 1992. He is an IEEE Fellow and recipient of the Computer Society’s Golden Core Award.

VDAT2006: 10th IEEE VLSI Design & Test Symposium
Date: August 9-12, 2006
Venue: International Centre, Goa, India
Organized by: VLSI Society of India
Industry Sponsors: TI India, Controlnet India, Intel India
In Cooperation With: IEEE-CS-TTTC, IEEE EDS/SSCS Bangalore Chapter, IEEE CAS Bangalore Chapter, IEEE Goa Chapter,Goa University

Call For Participation: Download Information Flyer ... Brochure

Tutorials: Three parallel tutorials T1, T2, and T3 will be run on Day-1 9 August 2006.
Tutorial – I Analog Design
Tutorial – II Low Power Electronics and Future Technologies
Tutorial – III Testing and Verification

Technical Tracks: VDAT symposium runs in three concurrent technical tracks:
1. Track on High-level Design will discuss issues related to system-level synthesis, microarchitecture, embedded systems, codesign, core-based design of SoC, timing convergence, high-level synthesis, logic synthesis, memory synthesis, and FPGA synthesis.

2. Track on Physical Design and VLSI Technology will discuss all issues related to physical design and process related aspects of integrated circuits, such as layout, fabrication, packaging, opto-electronic circuits, MEMS, deep submicron and nanometer devices.

3. Track on Testing and Verification will discuss issues related to testing, testability, and verification of digital designs, memories, analog designs, and mixed-signal designs, and circuits containing deep-submicron and nanometer devices.

Short Course on Digital Circuits Testing and Design for Testability

Conducted by: Dr. Nilanjan Mukherjee (Mentor Graphics Corporation) and Prof. Sudhakar M.Reddy (Iowa University)
Date: August 17 - 19, 2006
Venue: Hotel Atria, Palace Road, Bangalore, India
Organized by: VLSI Society of India
In cooperation with: IEEE Circuits and Systems Society, Bangalore Chapter

Registration: Download announcement with registration details

Abstract: Testing of every manufactured device is necessary to ensure product quality. As the complexity of electronic integrated circuits grows, their testing has also become very complex and expensive. This course will provide an overview of the recent trends in testing of digital circuits and designing these circuits for better testability.

About the speakers: Nilanjan Mukherjee received a B.Tech. (Hons) degree in Electronics and Electrical Communications Engineering from IIT Kharagpur, India, and a Ph.D. degree in Computer Engineering from McGill University, Montreal, Canada. He has been with Mentor Graphics since 1999 and is currently leading the Test Synthesis Group within the DFT division. He is a co-inventor of the Embedded Deterministic Test Technology and was a lead developer for TestKompress, the leading test compression tool in the industry. Prior to Mentor, he was with Bell Laboratories at Lucent Technologies.

Nilanjan has published over 35 technical papers at various international conferences and refereed journals. He received the Best Paper Award at the VLSI Test Symposium in 1995 and co-authored a paper that received the Best Student Paper award at the 2001 Asian Test Symposium. Nilanjan is a co-inventor of 20 US patents, some of which are pending approval.

Professor Sudhakar M. Reddy received the B.Sc. degree in Physics and the B.E. degree in Electronic Communications Engineering (ECE) from Osmania University, Hyderabad, the M.E. degree in ECE from the Indian Institute of Science, Bangalore, India, and the Ph.D. degree from the University of Iowa, Iowa City, Iowa. He joined the faculty of the Department of Electrical and Computer Engineering at the University of Iowa in 1968 where he is currently a University of Iowa Foundation Distinguished Professor of ECE. He served as the Chairperson of the ECE Department from 1981 to 2000.

Professor Reddy has published well over four hundred papers in archival journals and the proceedings of international conferences. Several papers co-authored by him received best paper nominations and awards. Professor Reddy has given keynote talks at international conferences. He has also given one-day tutorials to practicing engineers at international conferences. He received a Von Humboldt Prize in 1995 and the first Life Time Achievement Award from the International Conference on VLSI Design. Professor Reddy is a Life Fellow of IEEE.

Professor Reddy has served on the committees of several international conferences. He was the Technical Program Committee Chair of the 1989 Fault Tolerant Computing Symposium. He has served twice as a guest editor for the special issues on Fault Tolerant Computing and as an associate editor of the IEEE Transactions on Computers and has been serving as an associate editor of the IEEE Transactions on CAD for the last ten years.

Technical Talk on Design for Manufacturability of VLSI Circuits

PragaTI, IEEE Circuits and Systems Society Bangalore Chapter, and VSI jointly announce a Technical Talk

Speaker: Prof. Sandip Kundu (University of Massachusetts, Amherst)
Date: 19 July 2006
Time: 5.00 PM
Venue: TI Bangalore Auditorium

Registration: This talk is open to everyone. If you are not from TI India, please arrive at least 10 min before the start time so that we can take you through security.

About the speaker: Sandip Kundu: Sandip Kundu is Professor of Electrical and Computer Engineering at the University of Massachusetts, Amherst. Previously he was at Intel Corporation (till January 2005). Prior to joining Intel, he was a member of the research staff at the IBM T. J. Watson Research Laboratory (1988-1997). He has published over 70 papers and has given 12 tutorials in forums such as ICCAD, EDAC, DATE, ASP-DAC, ATS, ETW and ITC. Sandip has also been in numerous program committees including DAC, ICCAD, DATE and ICCD. He was the technical program chair for ICCD 2000, general chair in 2001. He was the general chair of VLSI conference in India in 2005. He is currently a Distinguished Visitor of IEEE Computer Society and an Associate Editor of IEEE Transactions on Computers.

Seminar on Game Theoretic Formulation for Wire Sizing Optimization in VLSI

PragaTI and IEEE Computer Society (Bangalore Chapter) jointly announce
a Seminar
Speaker: Prof. N. Ranagathan (University of South Florida)
Date: June 21, 2006 (Wednesday)
Time: 11.00 AM – 12.00 Noon
Venue: TI Bangalore Auditorium

Registration: This seminar is open to everyone and no formal registration is necessary. If you are coming from an organization other than TI India, please RSVP to and make sure that you are here at least 15 minutes before the seminar so that you can be taken through the reception to the venue.

Abstract: In this seminar, we propose a new methodology for wire sizing with simultaneous optimization of interconnect delay and crosstalk noise in deep submicron VLSI circuits. The wire sizing problem is modeled as an optimization problem formulated as a normal form game and solved using the Nash equilibrium. Game theory allows the optimization of multiple metrics with conflicting objectives. This property is exploited in modeling the wire sizing problem while simultaneously optimizing interconnect delay and crosstalk noise, which are conflicting in nature. The nets connecting the driving cell and the driven cell are divided into net segments. The net segments within a channel are modeled as players, the range of possible wire sizes forms the set of strategies and the payoff function is derived as the geometric mean of interconnect delay and crosstalk noise. The net segments are optimized from the ones closest to the driven cell towards the ones at the driving cell.

The complete information about the coupling effects among the nets is extracted after the detailed routing phase. The resulting algorithm for wire sizing is linear in terms of the number of wire segments in the given circuit. Experimental results on several medium and large open core designs indicate that the proposed algorithm yields an average reduction of 21.48% in interconnect delay and 26.25% in crosstalk noise over and above the optimization from the Cadence place and route tools without any area overhead. The algorithm performs significantly better than simulated annealing and genetic search as established through experimental results. A mathematical proof of existence for Nash equilibrium solution for the proposed wire sizing formulation is provided.

CLDW 2006: Custom LSI Design Workshop

Date: June 1-15, 2006
Venue: Goa, India
Organized by: VLSI Society of India, KarMic and ControlNet India Pvt Ltd
In cooperation with: IEEE Circuits and Systems Society, Bangalore Chapter and IEEE Goa Chapter
Venue: Government Engineering College, Farmagudi, Ponda - Goa

Registration: A uniform, non-refundable registration fee of Rs. 7000/- will be charged to participants. A discount of Rs 1000/- will be applicable to members of VSI – quote your VSI membership number and ensure that it is valid in June 2006. The fee includes simple accommodation, meals, and participation in the workshop with unlimited lab time. Travel and other expenses must be borne by the participant. A maximum of 30 participants will be admitted. Please send an application along with a Demand Draft payable to "VLSI Society of India" to be redeemable at Bangalore, India. Use the registration form attached.

Download Information Flyer and Registration Form

Introduction: In conjunction with ControlNet India and Karmic, VLSI Society of India announces a two-week intensive hands-on workshop on Custom LSI Design. The workshop is open to students and faculty with strong interest in VLSI. Preference will be given to students who have completed third year B.E./B.Tech or 1st year M.E/M.Tech. We encourage small groups of students and faculty from the same organization to apply to take full advantage of the workshop. The number of participants from a single organization will be limited by the committee.
It is expected that the participant is familiar with basics of electronics, MOS transistor operation, and has done some reading in MOS LSI. The workshop is intensive in hands-on activity and prior exposure to use of Linux/UNIX operating system is assumed. Certificates will be provided to participants from the VLSI Society of India upon successful completion of projects.

At the end of the workshop, the participant is expected to complete a design project, including its conceptualization, design, simulation, and custom layout implementation. There is a plan to fabricate successful projects from this effort through MOSIS ( Participants of selected projects will be given an opportunity at the VDAT Symposium ( to present their work.

In addition to custom LSI design experience, the participants will participate in group discussions and other team activities.

Seminar on MPEG: Audio - New Dimensions in Coding and Design
IEEE Circuits and Systems Society and Texas Instruments jointly announce
a Technical Seminar
Digital Multimedia Technical Seminar Series: Lecture #2
Speaker: Ashok Rao (IISc, Bangalore)
Date: April 28, 2006
Time: 12:57 PM
Venue: TI Bangalore Auditorium

Registration: The talk is open to Non-TIers. Please RSVP to Vidya Munirathnam and be present at least 15 minutes before the seminar begins so that you can be taken through our security to the auditorium.

Abstract: MPEG is now a popular Multimedia standard with significant success in productization. While it uses many cnventional schemes and techniques such as DCT, Huffman Code, Quantization etc., the significant impact of MPEG needs to be seen in the light of two major shifts in thinking:
1) the role of Biology (Life sciences) in Engineering products with major success and,
2) the attitude to solving problems (by coding) in a very efficient and diverse yet customizable manner.
The talk will look at MPEG Audio through this looking glass.

About the speaker: Dr Ashok Rao is the Head of the Network Project at CEDT, IISc Bangalore. He obtained his Ph.D from IIT Bombay in 1991 and has about 20 years of experience in DSP Teaching and Research.

Seminar on A video summarization enabled DVD Recorder

Texas Instruments and IEEE CAS Bangalore Chapter jointly announce
a Technical Seminar
Digital Multimedia Technical Seminar Series: Lecture #1
Speaker: Dr Ajay Divakaran (Mitsubishi Electric Research Laboratories)
Date: April 26, 2006 (Wednesday)
Time: 2.15 pm
Venue: TI Bangalore Auditorium, Room TR-1

Registration: Non-TIers may please RSVP to Vidya Munirathnam who has been copied on this mail and arrive at least 15 min before the seminar so that we can bring you into the seminar room after security procedures.

Abstract: The Personal Video Recorder such as Recordable-DVD Recorder, Blu-ray Disc Recorder and/or Hard Disc Recorder has become popular for a large volume storage device for video/audio content data and a browsing function that would quickly provide a desired scene to the user is required as an essential part of such a large capacity recording playback system.

We propose a highlight scene detection function by using only 'Audio' features and realize a browsing function for the recorder that enables completely automatic detection of sports highlights. We detect sports highlights by identifying portions with "commentator's excited speech" using Gaussian Mixture Models (GMM's) trained using the MDL criterion. Our computation is carried out directly on the MDCT coefficients from the AC-3 coefficients thus giving us a tremendous speed advantage. Our accuracy of detection of sports highlights is high across a variety of sports.

Our system was introduced into the Japanese market in the fall of 2005 and has been well received.

About the speaker: Ajay Divakaran received the B.E. (with Hons.) degree in Electronics and Communication Engineering from the University of Jodhpur, India in 1985, and the M.S. and Ph.D. degrees from Rensselaer Polytechnic Institute, Troy, NY in 1988 and 1993 respectively. He was an Assistant Professor with the ECE Department, University of Jodhpur , in 1985-86. He was a Research Associate at the ECE Department, Indian Institute of Science, in Bangalore in 1994-95. He was a Scientist with Iterated Systems Inc., Atlanta , GA from 1995 to 1998. He joined Mitsubishi Electric Research Laboratories (MERL) in 1998 and is now a Senior Team Leader - Senior Principal Member of Technical Staff.

He has been a key contributor to the MPEG-7 video standard. His current research interests include video and audio analysis, summarization, indexing and compression, and related applications. He has published several journal and conference papers, as well as six invited book chapters on video indexing and summarization. He has co-authored a book on video summarization. He has supervised four doctoral theses. He currently serves on program committees of key conferences in the area of multimedia content analysis. He currently leads the Data and Sensor Systems Team at the Technology Laboratory of MERL.

Technical Talk on Wireless Sensor Networks: A New Life Paradigm
TACT, VLSI Society of India, and IEEE CAS Bangalore Chapter announce
a Technical Talk
Speaker: Prof. Magdy Bayoumi (Louisiana)
Date: 20-February 2006
Time: 11.00 AM – 12.30 PM
Venue: TI Bangalore Auditorium


Abstract: Computers, Communication, and sensing technologies are converging to change the way we live, interact, and conduct business. Wireless Sensor networks reflect such convergence. These networks are based on collaborative efforts of a large number of sensor nodes. They should be low-cost, low-power, and multifunction. These nodes have the capabilities of sensing, data processing, and communicating. Sensor networks have wide range of applications, from monitoring sensors in industrial facilities to control and management of energy applications to military and security fields.

Because of the special features of these networks, new network technologies are needed for cost effective, low power, and reliable communication. These network protocols and architectures should take into consideration the special features of sensor networks such as: the large number of nodes, their failure rate, limited power, high density, etc. In this talk the impact of wireless sensor networks will be addressed, several of the design and communication issues will be discussed, and a case study of a current project of using such networks in drilling and management off-shore oil will be given.

About the speaker: Dr. Bayoumi has been a faculty member in CACS since 1985. Dr. Bayoumi has graduated 27 Ph.D. and about 150 Master's students. He has published over 300 papers in related journals and conferences. He edited, co-edited and co-authored 5 books in his research interests. He was and has been Editor, Associate Editor and Guest Editor in many prestigious journals, including Transactions on VLSI Systems, Transactions on Neural Networks, Transaction on Circuits and Systems II, and Journal of VLSI Signal Processing Systems. He has given numerous invited lectures and talks nationally and internationally, and has consulted in industry.

Dr. Bayoumi is Chair and Founder of "Circuits and Systems for Communication" Technical Committee of IEEE Circuits and Systems (CAS) Society. He won UL Lafayette 1988 Researcher of the Year award and 1993 Distinguished Professor award at UL Lafayette. Dr. Bayoumi is the recipient of the IEEE Circuits and Systems Society 2003 Education Award, and he is an IEEE Fellow.

ESLD2006: First International Workshop on Electronic System Level Design
Date: January 9-10, 2006
Venue: Golden Jubilee Seminar Hall, Department of ECE, Indian Institute of Science, Bangalore
Organized by: VLSI Society of India
In cooperation with: IEEE Circuits and Systems Society, Bangalore Chapter

Registration: Download Information Flyer and Registration Form

Organizing Committee:
C.P. Ravikumar, Texas Instruments, India
Suhas Hiwale, Poseidon Design Systems, Bangalore, India
Subodh Patil, Poseidon Design Systems, Bangalore, India
S. Jagannathan, Infineon, Bangalore, India
Bharadwaj Amruthur, Indian Institute of Science, Bangalore, India
Maria Adolf, Bluespec, Germany
Alok Kumar, Coware, Noida, India
Ashish Dixit, Tensilica, India
A. Vasudevan, Wipro Technologies, Bangalore, India

Abstract: Raising the level of abstraction to electronic system-level is emerging as a power solution to the problem of design productivity. ESL Design encompasses a number of disciplines, such as system system-level design entry, translation of high-level language descriptions to RTL, hardware-software partitioning, system-level verification, and system-level testing. A number of commercial products and associated methodologies are emerging for ESL Design. The goal of the workshop is to bring together a number of practitioners in the area of ESL Design and create a forum for exposing and discussing these methodologies.

The workshop will consist of keynote talks, invited presentations, embedded tutorials, exhibits, and a panel discussion.

Prof. Arvind, Massachusetts Institute of Technology, USA
Brian Bailey, Brian Bailey Consulting, USA
Prof. Rajesh Gupta, University of San Diego, California, USA
Dr. Rishiyur Nikhil, CTO, Bluespec Inc.
Dr. Shiv Tasker, CEO, Bluespec Inc.
Mr. Sarang Shelke, Director Technology, Poseidon Systems, Bangalore
Mr. Bill Salefski, VP Technology, Poseidon Systems, California
Mr. Viswanath Chakrala, Specialist VLSI System Design, Wipro Technologies, Bangalore
Mr. B.P.Srinivas, Senior Applications Engineer, Coware, Noida
Mr. Himanshu Sanghvi, Project Manager, Tensilica, California
Mr Nagendra Gulur Dwarakanath, Texas Instruments, India
Mr Badri Gopalan, Ageia, Bangalore
Mr Srinivasan Venkataraman, Synopsys, India
Mr Raghu Tupuri, General Manager (Silicon Design), Advance Micro Devices, Bangalore