IEEE - CAS Bangalore Chapter, India     
CAS Chapter - Region 10
Institute of Electrical and Electronics Engineers - Circuits and Systems Society
Goals: To conduct seminars, workshops, and other events pertaining to all aspects of electronic circuits and systems

Events - 2007

All links open in a New Window
IDV2007: Second International Workshop on Interconnect Design and Variability
Sponsored by: IEEE Circuits and Systems Society Bangalore Chapter
Organized by: VLSI Society of India
Date: December 13-14, 2007
Venue: Hotel Atria, Bangalore

Download announcement with registration form PDF 350KB
Deadline for early registration: November 30, 2007.

Targeted Audience:
The workshop will be useful to professionals as well as faculty and students who are looking for research topics.
Scope of the Workshop:
Interconnect scaling and variability are two difficult challenges in sub-100nm technology nodes. This workshop aims at addressing the following topics.
Latest advances in interconnect modeling and design innovations to continue performance scaling in sub- 100nm technologies:

  • Technology scaling trends
  • New process realities in sub-100nm technologies
  • Alternative interconnect methods
  • Interconnect analysis algorithms
  • Design and Architecture methods to mitigate RC scaling
  • In depth review of the latest advances in variability in sub-100nm technologies:
  • Device and interconnect process variations
  • Algorithms related to statistical analysis of performance and leakage
  • Practical approaches to address variability
  • Variation tolerant design methods

  • Speakers:
    Juan C. Rey (Mentor Graphics Corporation)
    Srinivas Mandavilli (Mentor Graphics India)
    Kazuya Masu (Tokyo Institute of Technology)
    Ersed Ackasu (OEA International Inc.)
    Noel Menezes (Intel Corporation)
    Sachin Sapatnekar (University of Minnesota)
    Tom Williams (Synopsys)
    Vish Sundararaman (Texas Instruments Inc. (Dallas)
    Steffen Rochel (Blaze DFM Inc.,)
    Nishath Verghese and Atul Sharan (Cadence Design Sys.)
    Nagaraj N.S. Texas Instruments Inc. (Dallas)
    Palkesh Jain and Gautam Kapila (Texas Instruments India)
    Madhav P. Desai (IIT Bombay)
    Vani Prasad (Freescale Semiconductor India)
    Vidyasagar Ganesan (AMD)

    IDV2006: First International Workshop on Interconnect Design and Variability

    Seminar on TI C2000 Digital Signal Controllers in Digital Motor Control and Digital Power Supplies
    PragaTI (TI India Technical University ) presents a seminar, Jointly with IEEE CAS Society Bangalore Chapter
    Speaker: Dr. Arefeen Mohammed (Texas Instruments)
    Date: November 26, 2007
    Time: 3:15 PM – 5:15 PM
    Venue: TI India Auditorium, Texas Instruments India, CV Raman Nagar Bangalore 560093

    The seminar is useful to anyone interested in embedded controls using DSP controllers. Practicing embedded engineers, engineers working in power electronics area, member of academics involved embedded system implementation and research will be benefited. Participants who are not Please RSVP to C.P. Ravikumar (ravikumar@ti. com) no later than Nov 23, 5.00 PM and must arrive no later than 3.00 PM on the day of the seminar. If multiple persons from the same organization are interested in attending, please collate the names and send a single mail.

    Abstract: In recent years, a new breed of processor known as the digital signal controller (DSC) has emerged. As the name implies, digital signal controllers from Texas Instruments Inc. combine the attributes of digital signal processors (DSPs) with those of microcontrollers (MCUs). These devices offer a system on chip solution by combining a DSP core with all the necessary power electronics peripherals like PWM, ADC, QEP etc. These C2000 digital controllers target motor control, power supply and other computationally demanding control-loop applications.

    This session presents the latest C2000 digital signal controllers from Texas Instruments Inc. in this rapidly growing field. The session highlights the latest innovations, and key distinctions of the C2000 digital controllers. The presentation will discuss both the hardware and the software aspects of the system design.

    About the speaker: Dr. Arefeen Mohammed is currently working as a system application engineer in Texas Instruments’ TMS320C2000 digital signal controller group. In this capacity, he is responsible for advancing TI’s embedded control collateral strategy, focusing on digital control of power electronics systems, as well driving C2000 controllers into new emerging end-equipments. Dr. Mohammed joined Texas Instruments in Houston , TX in 1995, and was one of the founding members of TI's digital motor control team.

    Dr. Mohammed has served as associate editor of IEEE Transactions on Power Electronics and IEEE Transactions of Industrial Electronics, has published over 70 technical papers in his fields. He has three patents and also several US patents pending. He received his B.S. from Bangladesh University of Engineering & Technology Dhaka, Bangladesh in 1987 and a M.S. and Ph.D. from Texas A&M University , College Station , TX in 1990 & 1994, all in electrical engineering.

    Seminar on System Level Design of Low Power Wireless Sensor Networks for Biomedical Applications
    IEEE Circuits and Systems Society Bangalore Chapter and ParagaTI (TI India Technical University) announce a seminar
    Speaker: Dinesh Bhatia (University of Texas, Dallas, USA)
    Date: September 17, 2007
    Time: 2:30 PM – 3:30 PM
    Venue: TI India Auditorium, Texas Instruments India, CV Raman Nagar Bangalore 560093

    The talk is open to everyone. Please RSVP to Sri Hari Prasad ( and arrive at least 15 minutes before the seminar to ensure seating. Refreshments will be served after the talk.

    Dinesh BhatiaAbout the speaker: Dinesh Bhatia is on the faculty of electrical engineering department at The University of Texas at Dallas . He directs research activities within the Embedded and Adaptive Computing group and is also a member of Center for Integrated Circuits and Systems at the University of Texas at Dallas . He received MS and a Ph.D. in Computer Science from the University of Texas at Dallas . His research interests include all aspects of reconfigurable and adaptive computing, architecture and CAD for field programmable gate arrays (FPGAs), physical design automation of VLSI Systems, biomedical electronics and systems, medical devices, natural energy scavenging and, applications of wireless sensor networks. His recent work on wireless sensor networks operating on scavenged energy is gaining importance in health care applications involving tele-medicine and remote health monitoring as well as in problems related to monitoring and alleviation of wood logging in forests.

    He has extensive experience in building large scale embedded and reconfigurable systems. Some of these activities include principal designer and investigator for RACE and NEBULA systems for Wright Laboratories of USAF, principal investigator for DARPA funded REACT program, Co-PI on AFRL funded SPARCs program and several more. He has published extensively in leading journals and conferences and continues to serve on program committees of several conferences. He is a senior member of IEEE, Computer Society, Circuits and Systems Society, Eta Kappa Nu, and recently served on the editorial board of IEEE Transactions on COMPUTERs. He is IEEE Circuits and Systems society’s distinguished lecturer for 2007.

    Seminar on Low Frequency and High Frequency Noise in Bipolar transistors
    Seminar jointly announced by PragaTI (TI India Technical University), VLSI Society of India, and IEEE Circuits and Systems Society (Bangalore Chapter)
    Speaker: Jayasimha Prasad (Maxim Integrated Products, USA)
    Date: August 23, 2007
    Time: 11.00 AM – 12.00 Noon
    Venue: TI India Auditorium, Texas Instruments India, CV Raman Nagar Bangalore 560093
    Download details in PDF 48KB

    This seminar is open to everyone – please send a confirmation to – Participants from organizations other than TI must arrive at the reception at least 15 minutes before the event to make it through the security.

    About the speaker: Prasad obtained his Ph.D in Electrical Engineering from Oregon State University, Corvallis. For the past twenty four years, he has been engaged in developing high-speed GaAs and SiGe HBT technology. He has been with Tektronix for 12 years developing GaAs-based HBT technology for high-speed oscilloscopes. He was a Tektronix Fellow and he was the first in the world to demonstrate a 60GHz InGaP HBT IC technology with 28ps gate delay. During the past 12 years, he has been with National Semiconductor, Micrel Semiconductor and Maxim Integrated Products where he has developed SiGe BiCMOS processes for wireless and fiber optic applications which have resulted in several products.

    Prior to the HBT work, Prasad has developed E2PROM processes at National Semiconductor and contributed to VMOS processes at AMI Semiconductor. Prasad is an IEEE Fellow and a Distinguished Lecturer of IEEE Electron Devices Society. He is member of the IEEE technical committees on Compound Semiconductor Devices, Compact Modeling and Education. He is currently serving in the IEEE Technical Field Awards Committees. Prasad has been serving in the technical committees of BCTM and IEDM. Prasad was an Adjunct Professor at Oregon State University. Currently, he is an adjunct faculty at Santa Clara University.

    Seminar on Scaling Commercial Model Checking to Larger Systems
    VLSI Society of India, IEEE Circuits and Systems Society Bangalore Chapter and
    PragaTI (TI India Technical University) jointly announce a seminar
    Speaker: Bob Kurshan (Cadence Design Systems)
    Date: 18 July 2007
    Time: 11.00 AM – 12.00 Noon
    Venue: TR-1, Texas Instruments India, CV Raman Nagar Bangalore 560093
    Download details in PDF 42KB

    This seminar is open to everyone. External participants must send a note to confirming their participation a week prior to the event. They must arrive at TI Bangalore reception area no later than 10.45 AM in order to be escorted in.

    About the speaker: Robert Kurshan joined Cadence Design Systems, Inc. as a Fellow, in 2001. He manages the Incisive Formal Engines Team, working closely with Cadence Berkeley Labs and multiple product groups. His work contributed greatly to Incisive Formal Verifier winning the Innovation of the Year award at Cadence in 2005. Prior to Cadence, he was a Distinguished Member of Technical Staff at Bell Laboratories, Murray Hill, NJ, until his retirement in 2001. He worked at Bell Labs since receiving his Ph.D from the University of Washington in mathematics in 1968, in homological algebra. Under special arrangement with Bell Labs, he spent two years as Visiting Professor at the Technion (Haifa, Israel) in the departments of Mathematics (1975-76) and Electrical Engineering (1984-85). He has taught courses at U.C. Berkeley and N.Y.U. At Bell Labs, he did research in periodic sequences, digital filtering and approximation theory, before he began work in formal verification in 1983.

    He is an author of over 80 technical publications, holds 22 patents in communications, digital filtering and verification, and is the author of the book "Computer-Aided Verification of Coordinating Processes" (Princeton Univ. Press, 1994), which is based upon a course he gave at U. C. Berkeley. In connection with his work in verification, he designed and built the COSPAN verification system together with Zvi Har'El, Ronald H. Hardin, and a number of others, based upon the theory that is developed in his book. COSPAN has been in use (and continuous development) since 1986, having been applied directly to a number of commercial projects inside AT&T, Lucent, NCR and Intel, as well as having been licensed to numerous universities for educational use. Currently, COSPAN is utilized by Cadence for commercial hardware verification as part of the Incisive Formal product line and for constraint-solving in its guided-random Incisive simulation.

    Five-day Course on Digital VLSI Design

    VLSI Society of India, IEEE Circuits and Systems Society Bangalore Chapter
    Conducted by:
    David Money Harris (Associate Professor, Harvey Mudd College of Engineering, CA, USA)
    Bharadwaj Amrutur, Assistant Professor, ECE Dept, Indian Institute of Science, Bangalore
    Date: July 23-27, 2007
    Time: 9.00 AM - 5.00 PM
    Venue: Golden Jubilee Hall, ECE Dept, Indian Institute of Science, Bangalore

    Registration: Registration is open to industry participants, faculty and postgraduate students of M.Tech programs related to VLSI.

    About the speakers: David Money Harris, Associate Professor, Harvey Mudd College of Engineering, CA, USA
    David Harris is an Associate Professor of Engineering at Harvey Mudd College. David received his Ph.D. from Stanford University in 1999 and his S.B. and M. Eng. degrees from MIT in 1994. His research interests include high speed CMOS VLSI design and computer arithmetic. He is the author or coauthor of CMOS VLSI Design: A Circuits and Systems Perspective, Logical Effort, Skew-Tolerant Circuit Design, and Digital Design and Computer Architecture. He holds twelve patents, has written numerous papers, and has designed chips at Sun Microsystems, Intel, Hewlett-Packard, and Evans & Sutherland. He has also served as an expert witness in patent litigation. When he is not teaching or building chips, David enjoys mountain climbing and hiking with his son.

    Bharadwaj Amrutur, Assistant Professor, ECE Dept, Indian Institute of Science, Bangalore
    Bharadwaj Amrutur got a B.Tech in CS&E from IIT Bombay at Mumbai in 1990 and a MS and PhD in EE from Stanford University in 1994 and 1999 respectively. His PhD thesis was on Fast Low Power SRAM Design. From 1999 to 2001, he was employed at Agilent Labs; Palo Alto, CA where he primarily worked on High Speed Chip to Chip interconnects. From 2001 to 2004, he was employed at Greenfield Networks, Sunnyvale, CA, where he worked on two networking ASICs for high-speed packet processing applications. Since 2004, he has been braving Bangalore Traffic and Roads, to teach in the ECE Department at Indian Institute of Science.

    Seminar on CyberWorkBench: C-based Behavioral Synthesis and Verification tools
    VLSI Society of India, IEEE Circuits and Systems Society Bangalore Chapter and
    PragaTI (TI India Technical University) jointly announce a PragaTI Seminar
    Speaker: Dr. Kazutoshi Wakabayashi (NEC Japan)
    Démonstration: Dr.Katsuharu Suzuki (Assistant manager)
    Date: March 23, 2007
    Time: 9.45 AM - 12.00 PM
    Venue: TI Bangalore Auditorium

    Registration: Lunch with opportunity to speak to the speakers : Please RSVP to Vivian Vancelet no later than March 20, 2007 5.00 PM. (

    Abstract: This talk introduces C-based Integrated System LSI Design Tool Suite called CyberWorkBench. We will explain several tools such as Behavioral synthesizer, formal verification (C-RTL equivalence checker, C-based property checker), RTL floor planner, HW-SW co-simulator capable of C-source debugging, and integrated GUI, and design flow. The CWB feature is "all-in-C" concept. CWB synthesize not only data intensive circuit but also control dominant circuit and control flow intensive circuit, so CWB enables designer to use only C language to design the whole SOC. Also, all design and verification processes can be done in the C-source code. The CWB is widely used in NEC group and some Japanese companies, and more than US$2Bilion chip are designed with CWB. We demonstrate various merits (e.g. design man power, design period, area, power, performance, reliability) with our commercial chip design experiences.

    About the speakers: Kazutoshi Wakabayashi received his B.E. and M.E. degrees from the University of Tokyo in 1984 and 1986. Dr of Engineering (from Univ. of Tokyo ). He joined NEC Corporation in Kawasaki Japan in 1986 and is currently a Senior Manager of System CAD Technology Group in Multimedia Research Laboratories. He was a visiting scientist at The Center for Integrated Systems at Stanford University during 1993 and 1994. He has been engaged in the research and development of VLSI CAD systems; high-level and logic synthesis, formal and semi-formal verification, system-level simulation, HDL, emulation, HLS and floor plan links, and reconfigurable computing. He received the Yamazaki-Teiichi Prize in 2004, and the IPSJ Convention Award in 1988, Sakai Kinen Special Award in 2001, and the NEC Distinguished Contribution Award in 1993 for his logic synthesis system and in 1999 for his formal verification system. He has served on the technical program committees of several international conferences and has been an editor of the Transactions of IEICE on VLSI CAD.

    Dr. Katsuharu Suzuki is an Assistant Manager in System CAD, System Devices Res.Labs, Central Res. Labs, NEC corporation.

    Seminar on Secure System-on-Chip and Embedded System Design

    PragaTI (TI India Technical University) and IEEE Circuits and Systems Society Bangalore Chapter jointly announce
    PragaTI Seminar
    Speaker: Dr. Anand Raghunathan (NEC Laboratories America)
    Date: Jan 5, 2007
    Time: 2.00 PM - 3.00 PM
    Venue: TI Bangalore Auditorium

    Registration: The seminar is open to everyone - no formal registration is necessary.

    Abstract: Our experiences with personal computers and the Internet have clearly identified information security as a paramount challenge. Embedded systems (consumer appliances such as mobile phones and MP3 players, automotive electronics, medical appliances, and ubiquitous devices such as sensors and RFID tags) are used pervasively in our lives. Such systems will contain our sensitive personal data, our identity, even our purchasing power, and perform several safety-critical functions. Unless addressed, security will become a concern that impedes the adoption of a wide range of electronic products, applications, and services. Several technologies have been developed for information security in computing and communication systems (cryptography, secure communication protocols, anti-virus tools, firewalls, intrusion detection, etc).

    These technologies are "functional" security measures, since they specify functions that must be added to the target system without any consideration of how they are embodied in hardware or software. Functional measures are certainly not sufficient to realize secure embedded systems in practice. Most real security attacks do not directly take on the theoretical strength of cryptographic algorithms; instead, they target weaknesses in their "implementation". Moreover, the embedded system designer must cope with security requirements in addition to other stringent design constraints (performance, power, cost, etc).

    In this talk, I will present an introduction to embedded system security challenges, and argue that effective security solutions can be realized only if they are built-in during the design of the constituent HW and SW components. The objectives of secure embedded system design will be defined from the HW/SW designer's perspective as addressing various "gaps" such as
    (i) the assurance gap, which refers to the gap between functional security measures and secure implementations,
    (ii) the security processing gap, which arises due to the processing requirements of the additional computations that must be performed for the purpose of security, and
    (iii) the battery gap, which is a consequence of the energy consumed in performing these computations.

    I will provide an overview of our research in this area, covering both secure SoC architectures, and methodologies that assist in their design. I will use the example of mobile appliances (mobile phones, PDAs) to concretely illustrate security challenges and solutions.

    About the speaker: Dr. Anand Raghunathan is a Senior Researcher at NEC Laboratories America, Princeton, NJ, where he leads research efforts on advanced system-on-chip architectures and design methodologies. His recent work has focused on the development of MOSES, a security solution for next-generation mobile appliances. He has also worked on various aspects of SoC and embedded system design methodologies, including system- level design and tools for power analysis and reduction. Anand has authored a book, six book chapters, over 150 conference and journal papers, and 20 U.S patents, and has presented several invited talks and conference tutorials in these areas. He has received six best paper awards at leading IEEE and ACM conferences, NEC's Patent of the Year and Technology Commercialization awards, and IEEE's meritorious service award. He was selected by MIT Technology Review among the "TR35" top young innovators in 2006 for his work on mobile security.

    He has served as Program Chair for the VLSI Test Symposium and the International Symposium on Low Power Electronics & Design, and as a member of the Program and Organizing Committees of several IEEE and ACM conferences. He has also served on the Editorial Board of IEEE Transactions on CAD, IEEE Transactions on VLSI, IEEE Design & Test of Computers, and the Journal of Low Power Electronics. Dr. Raghunathan received M.A. and Ph.D. degrees from Princeton University, and a B.Tech. degree from the Indian Institute of Technology, Chennai. He is a Golden Core member of IEEE Computer Society and a senior member of IEEE.

    ESLD2007: Second International Workshop on Electronic System Level Design

    January 11-12, 2007
    Wipro Learning Center, Electronics City, Bangalore
    Organized by: VLSI Society of India
    Corporate Sponsors: Wipro Technologies and ARM Embedded Technologies Pvt Ltd
    In cooperation with: IEEE Circuits and Systems Society, Bangalore Chapter

    Abstract: Raising the level of abstraction to electronic system-level is emerging as a power solution to the problem of design productivity. ESL Design encompasses a number of disciplines, such as system system-level design entry, translation of high-level language descriptions to RTL, hardware-software partitioning, system-level verification, and system-level testing. A number of commercial products and associated methodologies are emerging for ESL Design. The goal of the workshop is bring together a number of practitioners in the area of ESL Design and create a forum for exposing and discussing these methodologies.

    Organizing Committee:
    C.P. Ravikumar, Texas Instruments, India
    Suhas Hiwale, Poseidon, Bangalore
    Subodh Patil, Poseidon, Bangalore
    Bharadwaj Amruthur, Indian Institute of Science
    Maria Adolf, Bluespec, Germany
    Alok Kumar, Coware, Noida
    Ashish Dixit, Tensilica
    A. Vasudevan, Wipro Technologies
    Yogendra Rao, Wipro Technologies
    N.S. Murty, NXP Semiconductors

    Prof. Nikil Dutt, UC Irvine
    Dr. Rishiyur Nikhil, CTO, Bluespec Inc.
    Brian Bailey, Poseidon Design Systems
    Dr. Sachin Ghanekar, Tensilica
    Dr. Kanishka Lahiri, NEC-Labs
    Dr. Sandeep Shukla, Virginia Tech Univ.
    T.S. Rajesh Kumar, Texas Instruments Bangalore
    Aravinda Thimmapuram, NXP Semiconductors
    Desingh Balasubramanian, Poseidon
    Karthick Gururaj, NXP Semiconductors
    Srinivasan Venkataraman, Synopsys
    Amit Sharma, Synopsys
    Charles Hauck, VP Engineering, Bluespec Inc
    Zafar Ahmed K, ARM Embedded Technologies Pvt. Ltd

    T O P