IEEE - CAS Bangalore Chapter, India     CAS Chapter - Region 10
Institute of Electrical and Electronics Engineers - Circuits and Systems Society
Goals: To conduct seminars, workshops, and other events pertaining to all aspects of electronic circuits and systems

Events - 2017
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A Two-day Conference on ELECTRONICS MAKERS - 2017
Jointly organized by IEEE India Council, Centre for Embedded Product Design, Centre for Electronics Design & Technolgy, NSIT
In Association with IEEE-CAS, Bangalore Chapter
Date: July 1-2, 2017
Venue: Netaji Subhas Institute of Technology, New Delhi

Download Advance Technical Program (PDF)
With registration and Hostel accommdation details for those interested.

Download event announcement (PDF)


Registration: Prior registration is mandatory – please FILL OUT THE FORM no later than May 25, 2017.
There is a participation fee to cover the costs of the conference. The fee structure is mentioned in the above form. Please calculate the fee applicable to you and prepare a cheque or DD made out to "Centre for Embedded Product Design, NSIT" and send it to "Dr. Tarun Rawat, Electronics and Communication Engineering Division, Netaji Subhas Institute of Technology, Sector-3, Dwarka. New Delhi 110078" to reach no later than June 1. Your participation will be confirmed and further instructions will be sent through e-mail.

Hostel accommodation is available @ Rs 200/- per day. Please include this as part of registration fee and send a mail to Prof. Tarun Rawat ( intimating the time of your arrival and departure. Contact person for hostel is +919911686234. Hostel accommodation includes bedding. Meals are not included. However, meals can be purchased in the hostel or in the canteen. The conference will provide a working lunch and coffee/tea as part of registration fee.

Call for Participation: Industry professionals as well as students are welcome to submit their work to this two-day conference, which aims at creating a platform for innovation and Do-It-Yourself electronics. It is an oft-quoted statistic that by 2020, India will spend more than $400B in importing electronic technology/products. Do-It-Yourself and "Make-In-India" will surely help in bringing down this number and creating jobs in India in the core sectors of Electronics, Electrical, and Computer Engineering. Initiatives such as Open Source hardware and software as well as availability of low-cost semiconductor products are accelerating the growth of DIY. In this conference, the aim will be manifold - to discuss problems that DIYers tend to face, to provide networking opportunities for DIYers to help one another, and to provide a forum to showcase some of the recent innovations in Electronics DIY space.
Prizes will be provided to 3 best entries!

A One-day tutorial on Systems and Safety Engineering
Note: This event scheduled for 15 June, 2017 is temporarily postponed.

(IDIYE 2017)
Organized in cooperation with IEEE CAS Bangalore Chapter and IEEE Bangalore Section
Date: May 27, 2017
Time: 9.00 AM - 5.00 PM
Venue: Texas Instruments India, Bangalore Campus, Bangalore 560093
Conference General Chair: C.P.Ravikumar (Texas Instruments India)

Note: Submissions are closed.
Download Preliminary Advance Program (PDF) with registration details.

Keywords: "Do It Yourself", Innovation, "Make in India", "Electronic System Design and Manufacture (ESDM), Open Source, Maker

Introduction: It is estimated that by 2020, India’s import of electronic goods (including mobile phones and laptops) will exceed her import of oil. For job creation in India, we must design and manufacture electronic systems within the country. Innovation and expertise at electronic system-level is therefore essential. A change in engineering education is also necessary to impart the right system-level design/verification/test/validation skills to students. This 1-day conference will provide a forum for "Do It Yourself" enthusiasts from industries to present their ideas and demonstrate them in action.

The conference is intended for DIY-ers, faculty members and students from engineering colleges, who will benefit from the sharing of innovation and best practices. The conference will also provide opportunities for industry-academia interaction.


  • The topic of the conference concerns innovative electronic system design. It does not include chip design.
  • Accepted papers must be presented on May 27 and the projects must be demonstrated.
  • Certificates from IEEE will be provided to authors of all accepted papers.
  • It is OK to present/demo a project that has been discussed in other forums within the past year. No formal publication will be brought out and no copyright release will be sought. The presentation foils will be shared with the participants through Internet.
  • The authors are expected to submit foils describing their projects before April 25, 2017.
    • Please ensure that your submission does not contain any proprietary information.
    • There is no specific template for creating foils, but some guidelines are provided below.
    • Please include a Title Slide with Project title, names of authors and their affiliations.
    • Please include one slide on Problem Description that brings out the (societal) problem that your project addresses. This slide should bring out the importance of your work.
    • Please include one slide on Related Work that shows the limitations of existing solutions (e.g. cost/power/performance etc.).
    • Please bring out the implementation and innovation. We recommend that you upload a short (5-minute) video of the demo and provide a link in the PPT.
    • Please discuss the overall Contribution in one slide - where your work stands today, and how it is making/can make a difference.
    • References – 1 slide with references to papers/past DIY projects.
    • If your presentation is accepted, you are expected to attend the event and make the presentation as well as show a demo of the project. You are responsible for bringing your DIY project and make the necessary transport arrangements. For the purpose of demo, you will be provided a table with power supply and a pin-up board where 2 A3-sized posters can be pinned. There is no scope for only making presentations without a demo.
    • If there are multiple authors for a presentation, registration fee will be waived only for the presenting author.

    Submissions: The foils must be sent to with the subject line IDIYE-2017 submission before Apr 25, 2017. Confirmations will be sent to authors of accepted presentations before May 10, 2017.

    Preliminary Registration: It is important for all interested participants (including presenters) to register at the following website before Apr 25, 2017.

    IDIYE-2017 Preliminary Registration: (Closed) Click here to register before Apr 25, 2017.

    Final Registration to attend:

    • Prepare a DD (Demand Draft) for the amount applicable (IEEE Members: Rs.500.00/Non members: Rs.600.00) to "IEEE CAS Bangalore Chapter" payable at Bangalore. The DD is to be sent to: "C.P. Ravikumar, Secretary, IEEE CAS Bangalore Chapter, Texas Instruments, Bagmane Tech Park, CV Raman Nagar, Bangalore 560093" to reach us by May 16, 2017.
    • Please write your Name and Phone number on the reverse side of DD for our reference.
    • Send the scanned copy of the DD through mail to with a copy to as a safeguard, considering postal delay or any loss during transit
    • Alternatively you can also transfer the registration fee online through NEFT. Please download the Preliminary Advance Program (PDF) with registration details.

    A Seminar on CMOS Manufacturing in India – Issues and Challenges
    Organized by: PragaTI (TI India Technical University) In cooperation with IEEE CAS Society, Bangalore Chapter
    Speaker: HS Jatana (Sci/Engr 'SG', Group Head – Design & Process Grp, SCL /Dept of Space, Govt of India)
    Date: 25 April, 2017
    Time: 3.00pm - 4.00pm
    Venue: Texas Instruments India, Bagmane Techpark, CV Raman Nagar, Bangalore 93

    Registration: This seminar is open to IEEE members and non-members. There is no registration fee to attend this seminar. Please send an e-mail to before April 24, 2017 in the below format:

    Subject line: CMOS Seminar, April 25, 2017
    Please include the below details:
    Contact mail-address:
    Status: [student/faulty]
    Your participation will be confirmed and further instructions will be sent. Please take your seat a few minutes before the seminar begins.

    Abstract: The talk will focus on CMOS manufacturing activities in India, and will give brief details of Infrastructure and capability pertaining to CMOS manufacturing (design, process, etc), activities and research work carried out, academic interaction at SCL. Issues in managing fab operations, utilities required, fab ecosystem will be highlighted.
    As people from the academia will also be present, SCL-Academia scope of work can be discussed, and on what the academia can benefit from SCL.

    HS JatanaAbout the speaker: HS Jatana received his engineering education from BITS Pilani and had a brief stint at CMC Delhi as Software engineer wherein he worked on Railway Computerization Project, and later joined SCL in the CMOS division.
    He worked at Rockwell Semiconductor, California, USA where he was involved in design of R65 series of devices. He has worked in different areas of CMOS and has vast experience on CMOS design, Device testing / characterization, Test program development on ATE, Silicon debugging, and process Integration / porting over few technology nodes; starting from 5µm to sub-micron nodes. He also worked at AMS Austria for ten months on deputation for porting of SCL's CMOS processes at their foundry. Presently, as Group Head at SCL / ISRO is managing key divisions: VLSI Design, Process Development, Electro-optics devices.
    He has been instrumental in design of various ASICs and products viz, Energy meter chip, Single chip telephone, 12-bit ADC, 14-bit DAC, CMOS Imaging Sensor CIS, signal processor, SRAM, LVR, LDO's, RAdHARD devices etc. His areas of interest are low power CMOS design, analog design in DSM regime, process enhancements / optimization in DSM era. Has initiated many new process development modules like HV, SOI, BiCMOS, CCD process technology with back thinning, III-V materials on Si for photonics etc and APS for camera application, ultra-low power circuits (bias of few nA), rail-to-rail OTAs, RHDB SRAM etc.
    Also interested in spreading VLSI education and have delivered numerous lectures and tutorials on VLSI Design & Process Technology at ISRO centres, VECC (Dept of atomic energy), IISc Bangalore, IITs (Kharagpur, Madras, Bombay, Roorkee, Guwahati, Ropar), NITs (Hamirpur, Kurushetra, Manipur, Jaipur), NITTR Chandigarh, Assam State Technical university, Andhra University, Bangalore University, Panjab University, UIET-PU Chandigarh etc. He has also conducted a one-day tutorial at "17th VLSI Design and Test conference" (VDAT2015) and the "18th Conference" (VDAT2016). He is also conducting 'CMOS Analog Design' course for MTech students at IIST (Indian Institute of Space Technology) Trivandrum).
    He along with Dr GD Puri Head – Anaesthesia and Intensive care PGI Chandigarh has two patents to his credit for development of CLADS (Closed Loop Anaesthesia Drug Delivery System), which is being used on-line for critical surgeries like cardio vascular thoracic surgery.

    A Seminar on
    From Power Management to Energetic Intelligence: An evolutionary challenge for students, educators and designers
    Organized by: IEEE CAS Bangalore Chapter in cooperation with PragaTI (TI India Technical University)
    Speaker: Nicola Femia (University of Salerno, Italy)
    Date: 10 April, 2017
    Time: 11:00 AM to 12:00 PM
    Venue: Texas Instruments India, Bagmane Techpark, CV Raman Nagar, Bangalore 93

    Registration: This seminar is open to IEEE members and non-members. There is no registration fee to attend this seminar. Please write to to enroll. Your participation will be confirmed by April 7 and further details will be sent.

    Abstract: Power Management Circuits and Systems provide electrical energy to all the objects making our life more comfortable, safer and funnier, like smart phones and watches, aircraft and automobiles, implanted prostheses and magnetic resonance machines, blenders and microwave ovens, robots and drones, digital TV sets and personal computers. The Design of Power Management Circuits and Systems is an exciting intellectual dare for students and educators, as it stimulates insight of interdisciplinary knowledge, understanding of new technologies, exploration of unconventional design solutions, discovery of the power of mathematics, reinforcement of problem solving capability, intelligent use of the energy and ultimately preservation of the environment and of the Earth's resources.
    Power Management Circuits and Systems have today to implement much more enhanced energy processing functions than in the past, thus bridging power designers into the era of Energetic Intelligence. University education and industry training has to coherently enhance, to proactively drive this evolution and to guide talented students and designers towards the achievement of powerful professional skills. The seminar intends to overview power management design issues and to propose a vision of the knowledge and tools needed to win the challenges of Energetic Intelligence.

    Nicola FemiaAbout the speaker: Nicola Femia is Full Professor at the University of Salerno, Italy, where he teaches Power Electronics and Energetic Intelligence. His research activities encompass circuit theory and applications, design and optimization of switching power supplies, magnetic power components modeling and optimization, power electronics and control techniques for photovoltaic systems, wireless power transfer systems. He has co-authored more than 150 technical papers on power electronics topics and five patents on photovoltaic control techniques. He leads the Power Electronics and Renewable Sources Laboratory of the Computer and Electrical Engineering and Applied Mathematics Department of the University of Salerno.
    He has directed many research projects in collaboration with worldwide leader companies, including Texas Instruments, National Semiconductor, Power-One/ABB, On Semiconductor, Whirlpool, STMicroelectronics, Coilcraft. Since 2001 he has delivered industry Power Electronics Design and Optimization courses and seminars, in Europe and United States, in collaboration with National Semiconductor, Texas Instruments, Silica/AVNET, Coilcraft. In 2014 he has been Visiting Professor in the Electrical Engineering (EE) Department of the Stanford University, Stanford, CA, where he taught Power Electronics Control and Energy Aware Design in the EE Enhanced Master Program. He is author and co-creator of the Texas Instruments Power Management Laboratory Kit (TI-PMLK).

    A One-day Course on Analog System Design
    Organized by: IEEE-CAS Society, Bangalore Chapter in cooperation with Texas Instruments India
    We thank Chitkara University (Punjab and Himachal Pradesh) for supporting this event.
    Speaker: Dr. K.Radhakrishna Rao (TI India), Co-faculty: Sagar Juneja (Chitkara Univ.)
    Date: March 18, 2017
    Time: 9.00 AM - 5.00 PM
    Venue: Texas Instruments India, Bangalore Campus, Bangalore 560093

    Registration: This hands-on course intended for college teachers and student members of IEEE only.
    A course fee of Rs 500/- per person will be applicable, which will cover lunch and coffee.
    Write to (with a copy to with the following details before February 28, 2017.

      1. Full name of participant
      2. Status: Student/Faculty
      3. College:
      4. College ID is valid up to:
      5. IEEE membership number:
      6. IEEE membership valid up to:
    The fee needs to be paid to "IEEE CAS Bangalore Chapter" before March 5, 2017 by DD or Cheque. The DDs/Cheques can be sent to:
    C.P. Ravikumar, Secretary, IEEE CAS Bangalore Chapter, Texas Instruments, Bagmane Tec Park, CV Raman Nagar, Bangalore 560093

    - If your registration is confirmed, you must pay the fee by March 10 (instructions will be sent).
    - If the payment is not received by March 10, your registration will not be confirmed.

    Abstract: Analog design has become a key part of modern SoC. Even embedded microcontrollers include some analog IP such as operational amplifiers, ADC, DAC, power regulators, oscillators, etc. In this 1-day course, the participants will get a hands-on introduction to analog system design. The course will include lectures as well as hands-on exercises. Participation certificates will be issued to participants at the end of the day.
    This program is intended only for teachers and students who are members of IEEE. The participants must have taken a course on linear integrated circuits/analog circuits.

    About the speakers:
    Dr.K Radhakrishna Rao is with Texas Instruments for the past 10 years as a part of the talent development team. Prior to joining TI, he spent over 30 years at IIT Madras as part of the faculty of Electrical Engineering Department.
    He has published numerous papers in the area of pure analog design. He has taught a number of courses related to analog design both at IIT Madras and Texas Instruments. At TI, he helped design the Analog System Lab Kit and coauthored the "Analog System Lab Manual" which are popularly used in engineering colleges across the world. He has recorded several popular video courses for NPTEL in the area of analog circuit design.

    Sagar Juneja is currently a Research Associate at Chitkara University Research & Innovation Network (CURIN), Chitkara University, Himachal Pradesh.

    A Two-day Workshop entitled Science Editathon
    Organized by: IEEE-CAS Bangalore Chapter, In cooperation with Wikipedia Foundation and Texas Instruments, India
    Date: 4-5 February, 2017
    Time: 9.00AM to 5.00PM
    Venue: Texas Instruments India, Bangalore Campus

    Registration: The workshop is open to all IEEE members. Please register by writing to Your participation will be confirmed and further instructions will be mailed to you. All participants are expected to add at least one science article to Wikipedia.

    Abstract: Wikipedia is a great source of information in the 21st century. The intent of this workshop is to educate participants on how to edit Wikipedia articles on science-related topics.
    On Day-1, those who do not have Wikipedia accounts will create one for themselves and will be given an overview of how to add articles into Wikipedia and edit articles added by others. Best practices of writing and editing will be shared. In particular, the goal of this workshop is to add articles in Indian languages such as Kannada.

    A Seminar on Authentication and Functional Obfuscation of Integrated Circuits
    Organized by: PragaTI (TI India Technical University) In cooperation with IEEE CAS Society, Bangalore Chapter
    Speaker: Prof. Keshab K. Parhi (Dept of ECE, University of Minnesota, Minneapolis)
    Date: January 13, 2017
    Time: 2:00 PM to 3:00 PM
    Venue: LC-2, TI India BTP Office, Bagmane Tech Park, CV Raman Nagar, Bangalore 560093

    Registration: This seminar is open to members of IEEE. Please call 080-25099727 and leave a message to confirm your participation. Please bring a photo-id to gain entrance. Limited parking is available for visitors.

    Abstract: The talk will focus on the important aspect of hardware security. Prof. Parhi will discuss the recent results that his team has unearthed in this area in two parts.
    Physical unclonable functions (PUFs) are small circuits that can exploit manufacturing process variations to generate unique signatures of chips. These unique signatures, in the form of challenge-response pairs, can be stored in a server and can be used to authenticate devices. Various delay-based PUFs include multiplexer (MUX) PUF and ring-oscillator PUF. Examples of memory PUFs include SRAM PUF and DRAM PUF. The speaker will talk about modeling both linear and nonlinear MUX PUFs, and will show that both hard and soft responses of linear and nonlinear MUX PUFs can be modeled by artificial neural network.
    The second part of the talk will be about functional obfuscation where the functionality is hidden by incorporating keys to a design such that the circuit only functions correctly if the key is correct. Various modes are introduced such that only the correct key triggers the correct functionality of the chip. One goal is to prevent foundries from manufacturing excess parts and selling in black market, Another goal is to prevent theft of intellectual property. A third goal of obfuscation is to prevent reverse engineering. The speaker will introduce the notions of fixed and dynamic obfuscation. We will show that the time to find the key by trial and error can be increased exponentially with dynamic obfuscation.

    Prof. Keshab K. ParhiAbout the speaker: Keshab K. Parhireceived the B.Tech. degree from the Indian Institute of Technology (IIT), Kharagpur, in 1982, the M.S.E.E. degree from the University of Pennsylvania, Philadelphia, in 1984, and the Ph.D. degree from the University of California, Berkeley, in 1988. He has been with the University of Minnesota, Minneapolis, since 1988, where he is currently Distinguished McKnight University Professor and Edgar F. Johnson Professor in the Department of Electrical and Computer Engineering.
    He has published 600 papers, is the inventor of 29 patents, and has authored the textbook VLSI Digital Signal Processing Systems (Wiley, 1999) and coedited the reference book Digital Signal Processing for Multimedia Systems (Marcel Dekker, 1999). Dr. Parhi is widely recognized for his work on high-level transformations of iterative data-flow computations, for developing a formal theory of computing for design of digital signal processing systems, and for his contributions to multi-gigabit Ethernet systems on copper and fiber and for backplanes.
    His current research addresses VLSI architecture design of signal processing, communications and biomedical systems, error control coders and cryptography architectures, high-speed transceivers, stochastic computing, hardware security, and molecular computing. He is also currently working on intelligent classification of biomedical signals and images, for applications such as seizure prediction and detection, schizophrenia classification, biomarkers for mental disorders, brain connectivity, and diabetic retinopathy screening.
    Dr. Parhi is the recipient of numerous awards including the 2012 Charles A. Desoer Technical Achievement award from the IEEE Circuits and Systems Society, the 2004 F. E. Terman award from the American Society of Engineering Education, the 2003 IEEE Kiyo Tomiyasu Technical Field Award, the 2001 IEEE W. R. G. Baker prize paper award, and a Golden Jubilee medal from the IEEE Circuits and Systems Society in 2000. He is a Fellow of IEEE (1996). He served as the Editor-in-Chief of the IEEE Trans. Circuits and Systems, Part I during 2004-2005, and as an elected member of the Board of Governors of the IEEE Circuits and Systems society from 2005 to 2007.
    For more information on the speaker, visit

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