IEEE - CAS Bangalore Chapter, India     CAS Chapter - Region 10
Institute of Electrical and Electronics Engineers - Circuits and Systems Society
Goals: To conduct seminars, workshops, and other events pertaining to all aspects of electronic circuits and systems

Events - 2017
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December
C-CUBE 2017: IEEE Second International conference on Circuits, controls and communications
Organized by: R N Shetty Institute of Technology, with Technical co-sponsorship from: IEEE Bangalore section, IEEE CAS Society Bangalore chapter, IEEE CIS Society Bangalore chapter, IEEE COMSOC Society Bangalore chapter
Date: December 15-16, 2017
Venue: RNSIT, Channasandra, Rajarajeshwari Nagar post, Dr.Vishnuvardhan Road, RR Nagar post, Bangalore 560098, Karnataka, India

Visit Conference web site for further details.


November
A Seminar on Current Research in Power Electronics
Organized by: IEEE Circuits and Systems Society Bangalore Chapter and IEEE Power Electronics Society, Bangalore Chapter, in association with Texas Instruments (India)
Speaker: Dr. Kaushik Basu (Department of Electrical Engineering, Indian Institute of Science, Bangalore)
Date: November 29, 2017
Time: 3.00PM - 4.00PM
Venue: Texas Instruments (India), Bangalore Campus, Bagmane Techpark, CV Raman Nagar

Registration: This seminar is open to IEEE members and non-members, and will be also available as a live webinar for those who wish to attend it from a remote location. Please register at
https://docs.google.com/forms/d/e/1FAIpQLScuLoHkdD9s2bWaM4fqsHqGhpNTu7obfdfI4HDX-d4wKUoS0w/viewform?usp=sf_link
and indicate whether you wish to attend in person or remotely. Please complete the registration no later than November 25. Further instructions will be sent by November 27 through e-mail.

Abstract: In this talk, I will present some of the research projects that we are currently working on at the Department of Electrical Engineering, Indian Institute of Science, along with some of the power electronic hardware that has been developed. I will present few of the recently developed power converter topologies along with modulation strategies that result in power-efficient, cost efficient, reliable and low footprint solutions for the grid integration of utility-scale solar. A solution for direct interconnection to medium-voltage grid integration will be presented. Other research topics include split-phase induction machine drive, hardware emulation of flexible transmission line, analytical loss estimation of SiC devices and gate driver design of iGaN540, a normally-on GaN switch developed at the Indian Institute of Science. I will also speak about our recent work on hardware development, which includes an SoC-based embedded platform and a Si IGBT-based modular converter.

Kaushik BasuAbout the speaker: Dr.Kaushik Basu received his B.E. degree from the Bengal Engineering and Science University, Shibpore, India, in 2003, an M.S. degree in electrical engineering from the Indian Institute of Science, Bangalore, India, in 2005, and a Ph.D. degree in electrical engineering from the University of Minnesota, Minneapolis, in 2012, respectively. He was a Design Engineer with Cold Watt India in 2006 and an Electronics and Control Engineer with Dynapower Corporation USA from 2013-15. Currently he is an Assistant Professor in the Department of Electrical Engineering in Indian Institute of Science. He is an author and co-author of several technical papers published in peer-reviewed journals and conferences. His research interests are in the area of Power Electronics.


October
A Primer on Machine Learning and Artificial Neural Networks
Organized by: PragaTI (TI India Technical University) in association with IEEE-CAS Society, Bangalore Chapter
Speaker: Osheen Nayak (Texas Instruments)
Date: 24 October 2017
Time: 2.00 PM - 5.00 PM IST
Venue: Texas Instruments India, Bangalore Campus, LC-2, Bagmane Techpark, CV Raman Nagar, Bangalore 560093

Registration: This seminar is open to IEEE members and non-members. There is no registration fee to attend this seminar, but prior registration is mandatory. Limited seats are available. Please fill out the online registration form at https://docs.google.com/forms/d/e/1FAIpQLSfYp2h2n0FUq_X9tno8BHZx5YIQrYVWTcI1R1556RT64ZD-cA/viewform?c=0&w=1 before 21 October 2017.

NOTE: Due to a large number of registrations, the above form is now closed. Owing to the limited seats available, the selected registered participants from the list will be intimated by e-mail.

Those who wish to join the seminar through telecom may use:
1. http://ti.webex.com and enter the meeting number: 715 367 304
-OR-
2. For voice, dial 18002660444 Or 18004259996, and use the passcode 34257077

Abstract: The talk will cover

  • Introduction to machine learning – supervised learning, unsupervised learning and key terminologies.
  • Linear Regression with single and multiple variables, gradient descent algorithm and regularization.
  • Logistic Regression techniques.
  • Introduction to various algorithms such as decision trees, k-Nearest Neighbors, Support Vector Machines.
  • Applying machine learning in python.
  • Representation of artificial neural networks and back propagation algorithm.

  • September
    A Seminar on Challenges in Developing Semiconductors for Power Products
    Jointly Organized by IEEE Power Electronics Society and IEEE CAS Bangalore Chapter
    Speaker: Ebenezer Vidyasagar (Director APP, TI India)
    Date: 7 September 2017
    Time: 2.30PM - 3.30PM
    Venue: Seminar Hall, DESE, Indian Institute of Science, Bangalore

    Registration: The seminar is open to students, teachers, and IEEE members. There is no fee to attend the seminar, but registration is needed. Your registration will be confirmed and further details will be sent.
    Limited seats are available. Please register online no later than 30 August 2017. Your participation will be confirmed by 31 August.
    Refreshments will be served at the end of the seminar.

    Abstract: Providing electrical power to modern-day electronic systems is in itself a challenging task due to the complexity of these systems. The number of transistors in these systems has been steadily increasing, resulting in an increased need for power, necessitating power management. Systems integrate diverse IP from multiple vendors, including digital, analog and mixed-signal IP, which require different levels of power. Increasingly, many electronic systems operate on battery power and harvested energy. Further, it is important to consider the footprint of the solution and thermal dissipation when powering modern gadgets. TI offers complete power solutions with a full line of high-performance products, ranging from standard linear regulators to highly efficient DC/DC converters and battery management ICs. This talk will focus on several technology challenges that we face as we move from discrete power solutions to fully integrated monolithic power solutions. The talk is intended for postgraduate students in Electrical/Electronics engineering. It is also open to interested members of IEEE.

    Ebenezer Vidyasagar, TI India)About the speaker: Ebenezer Vidyasagar is the Director of APP (Analog Power Products) Engineering Team at Texas Instruments. He has over 20 years of experience in driving successful product development across hardware and software on a global scale. He has lead engineering functions of applications and development in hardware and software operations. He has been recognized for his ability to identify continuous change actions to improve efficiency, reduce cost, enhance quality, and increase people engagement. He has held several positions with an outstandiang track record of awards and promotions. Ebenezer has a Master's degree from CEDT, IISc and was a Gold Medalist of the Master’s Program at CEDT in IISc.


    August
    A Seminar on Analog Design and Test - Challenges and Opportunities
    Organized by: IIIT Bangalore in association with IEEE-CAS Society, Bangalore Chapter
    Speaker: Dr.C.P.Ravikumar (Texas Instruments India)
    Date: 30 August 2017
    Time: 2.30pm to 3.30pm
    Venue: IIIT Bangalore, 26/C, Electronics City, Hosur Road, Bangalore 560100

    Registration: This seminar is open to IEEE members. There is no registration fee to attend this seminar. Please send an e-mail to registration@ieee-cas-bangalore.org before 29 August 2017 with your name, organization, phone no. and contact address. Your participation will be confirmed and further instructions will be sent.

    Abstract: Although most of the signal processing is carried out in digital domain today, analog and mixed-signal circuits are essential in the signal chain of a system. An analog front-end is needed to improve the signal-to-noise ratio and strengthen the signal coming from a sensor.  Data converters are needed to transform data from analog to digital domain and vice versa. Power management circuits such as DC-DC converters and voltage regulators are essential in an SoC which has multiple voltage islands. Clock generators are needed because we have multiple frequency domains in an SoC. Design, verification and testing of analog and mixed-signal circuits pose many challenges. In this paper, we will discuss the importance of understanding analog sub-system design at the system-level of abstraction. We will make recommendations on some changes that are needed in the way analog design is taught today, so as to bridge the gap between industry and academia.

    Dr.C.P.Ravikumar (Texas Instruments India)About the speaker: C.P. Ravikumar is presently the Director of Technical Talent Development at Texas Instruments, India. He leads the TI India Technical University which provides learning opportunities to employees of TI India. His earlier roles in TI include Director of University Relations and Senior Technologist (VLSI Test).  He is also an adjunct faculty at IIT Madras.  Before joining TI India in 2001, Ravikumar was a Professor of Electrical Engineering at the Indian Institute of Technology, Delhi (1991-2001). He also held a visiting position at the University of Southern California (1995-1996) and the position of Vice President (Training) atControlnet India Pvt Ltd (2000-2001).  He obtained his Ph.D. (Computer Engineering) from the University of Southern California (1991), M.E. in Computer Science with highest scores from Indian Institute of Science (1987) and B.E. in Electronics with a Gold Medal from Bangalore University (1983).
    He has published over 200 papers in leading International conferences and journals. He founded the VLSI Design and Test Symposium (VDAT) and was the General Chair of this event for 15 years, from its inception in 1998 to 2011. He is the author/editor/coauthor of over 12 books in areas of VLSI and has contributed several book chapters.  He is the editor of the Journal of VLSI and Electronic System Design and on the editorial board of the Journal of Electronic Testing – Theory and Applications and the Journal of Low Power Electronics. He has won the best paper award at IEEE International Conference on VLSI Design (2002) and VLSI Test Symposium (2005). He is a Senior Member of IEEE, honorary secretary of IEEE CAS Bangalore chapter (2004-current) which he founded, and the honorary secretary of VLSI Society of India (2003-2011). He received an award from Zinnov for his work on eco-system development in India (Universities).


    July
    A Two-day Conference on ELECTRONICS MAKERS - 2017
    Jointly organized by IEEE India Council, Centre for Embedded Product Design, Centre for Electronics Design & Technolgy, NSIT
    In Association with IEEE-CAS, Bangalore Chapter
    Date: July 1-2, 2017
    Venue: Netaji Subhas Institute of Technology, New Delhi

     
    Download Advance Technical Program (PDF)
    With registration and Hostel accommdation details for those interested.
     

    Download event announcement (PDF)

    ELECTRONICS MAKERS - 2017

    Registration: Prior registration is mandatory – please FILL OUT THE FORM no later than May 25, 2017.
    There is a participation fee to cover the costs of the conference. The fee structure is mentioned in the above form. Please calculate the fee applicable to you and prepare a cheque or DD made out to "Centre for Embedded Product Design, NSIT" and send it to "Dr. Tarun Rawat, Electronics and Communication Engineering Division, Netaji Subhas Institute of Technology, Sector-3, Dwarka. New Delhi 110078" to reach no later than June 1. Your participation will be confirmed and further instructions will be sent through e-mail.

    Hostel accommodation is available @ Rs 200/- per day. Please include this as part of registration fee and send a mail to Prof. Tarun Rawat (tarundsp@gmail.com) intimating the time of your arrival and departure. Contact person for hostel is +919911686234. Hostel accommodation includes bedding. Meals are not included. However, meals can be purchased in the hostel or in the canteen. The conference will provide a working lunch and coffee/tea as part of registration fee.

    Call for Participation: Industry professionals as well as students are welcome to submit their work to this two-day conference, which aims at creating a platform for innovation and Do-It-Yourself electronics. It is an oft-quoted statistic that by 2020, India will spend more than $400B in importing electronic technology/products. Do-It-Yourself and "Make-In-India" will surely help in bringing down this number and creating jobs in India in the core sectors of Electronics, Electrical, and Computer Engineering. Initiatives such as Open Source hardware and software as well as availability of low-cost semiconductor products are accelerating the growth of DIY. In this conference, the aim will be manifold - to discuss problems that DIYers tend to face, to provide networking opportunities for DIYers to help one another, and to provide a forum to showcase some of the recent innovations in Electronics DIY space.
    Prizes will be provided to 3 best entries!


    June
    A One-day tutorial on Systems and Safety Engineering
    Note: This event scheduled for 15 June, 2017 is temporarily postponed.

    May
    (IDIYE 2017)
    A One-day conference on INNOVATION & DO-IT-YOURSELF ELECTRONICS
    Organized in cooperation with IEEE CAS Bangalore Chapter and IEEE Bangalore Section
    Date: May 27, 2017
    Time: 9.00 AM - 5.00 PM
    Venue: Texas Instruments India, Bangalore Campus, Bangalore 560093
    Conference General Chair: C.P.Ravikumar (Texas Instruments India)
    ravikumar@ti.com

    Note: Submissions are closed.
    Download Preliminary Advance Program (PDF) with registration details.

    Keywords: "Do It Yourself", Innovation, "Make in India", "Electronic System Design and Manufacture (ESDM), Open Source, Maker

    Introduction: It is estimated that by 2020, India’s import of electronic goods (including mobile phones and laptops) will exceed her import of oil. For job creation in India, we must design and manufacture electronic systems within the country. Innovation and expertise at electronic system-level is therefore essential. A change in engineering education is also necessary to impart the right system-level design/verification/test/validation skills to students. This 1-day conference will provide a forum for "Do It Yourself" enthusiasts from industries to present their ideas and demonstrate them in action.

    The conference is intended for DIY-ers, faculty members and students from engineering colleges, who will benefit from the sharing of innovation and best practices. The conference will also provide opportunities for industry-academia interaction.

    Guidelines:

  • The topic of the conference concerns innovative electronic system design. It does not include chip design.
  • Accepted papers must be presented on May 27 and the projects must be demonstrated.
  • Certificates from IEEE will be provided to authors of all accepted papers.
  • It is OK to present/demo a project that has been discussed in other forums within the past year. No formal publication will be brought out and no copyright release will be sought. The presentation foils will be shared with the participants through Internet.
  • The authors are expected to submit foils describing their projects before April 25, 2017.
    • Please ensure that your submission does not contain any proprietary information.
    • There is no specific template for creating foils, but some guidelines are provided below.
    • Please include a Title Slide with Project title, names of authors and their affiliations.
    • Please include one slide on Problem Description that brings out the (societal) problem that your project addresses. This slide should bring out the importance of your work.
    • Please include one slide on Related Work that shows the limitations of existing solutions (e.g. cost/power/performance etc.).
    • Please bring out the implementation and innovation. We recommend that you upload a short (5-minute) video of the demo and provide a link in the PPT.
    • Please discuss the overall Contribution in one slide - where your work stands today, and how it is making/can make a difference.
    • References – 1 slide with references to papers/past DIY projects.
    • If your presentation is accepted, you are expected to attend the event and make the presentation as well as show a demo of the project. You are responsible for bringing your DIY project and make the necessary transport arrangements. For the purpose of demo, you will be provided a table with power supply and a pin-up board where 2 A3-sized posters can be pinned. There is no scope for only making presentations without a demo.
    • If there are multiple authors for a presentation, registration fee will be waived only for the presenting author.

    Submissions: The foils must be sent to ravikumar@ti.com with the subject line IDIYE-2017 submission before Apr 25, 2017. Confirmations will be sent to authors of accepted presentations before May 10, 2017.

    Preliminary Registration: It is important for all interested participants (including presenters) to register at the following website before Apr 25, 2017.

    IDIYE-2017 Preliminary Registration: (Closed) Click here to register before Apr 25, 2017.

    Final Registration to attend:


    • Prepare a DD (Demand Draft) for the amount applicable (IEEE Members: Rs.500.00/Non members: Rs.600.00) to "IEEE CAS Bangalore Chapter" payable at Bangalore. The DD is to be sent to: "C.P. Ravikumar, Secretary, IEEE CAS Bangalore Chapter, Texas Instruments, Bagmane Tech Park, CV Raman Nagar, Bangalore 560093" to reach us by May 16, 2017.
    • Please write your Name and Phone number on the reverse side of DD for our reference.
    • Send the scanned copy of the DD through mail to accounts@ieee-cas-bangalore.org with a copy to registration@ieee-cas-bangalore.org as a safeguard, considering postal delay or any loss during transit
    • Alternatively you can also transfer the registration fee online through NEFT. Please download the Preliminary Advance Program (PDF) with registration details.


    April
    A Seminar on CMOS Manufacturing in India – Issues and Challenges
    Organized by: PragaTI (TI India Technical University) In cooperation with IEEE CAS Society, Bangalore Chapter
    Speaker: HS Jatana (Sci/Engr 'SG', Group Head – Design & Process Grp, SCL /Dept of Space, Govt of India)
    Date: 25 April, 2017
    Time: 3.00pm - 4.00pm
    Venue: Texas Instruments India, Bagmane Techpark, CV Raman Nagar, Bangalore 93

    Registration: This seminar is open to IEEE members and non-members. There is no registration fee to attend this seminar. Please send an e-mail to registration@ieee-cas-bangalore.org before April 24, 2017 in the below format:

    Subject line: CMOS Seminar, April 25, 2017
    Please include the below details:
    Name:
    Contact mail-address:
    Organization:
    Status: [student/faulty]
    Interest:
    Your participation will be confirmed and further instructions will be sent. Please take your seat a few minutes before the seminar begins.

    Abstract: The talk will focus on CMOS manufacturing activities in India, and will give brief details of Infrastructure and capability pertaining to CMOS manufacturing (design, process, etc), activities and research work carried out, academic interaction at SCL. Issues in managing fab operations, utilities required, fab ecosystem will be highlighted.
    As people from the academia will also be present, SCL-Academia scope of work can be discussed, and on what the academia can benefit from SCL.

    HS JatanaAbout the speaker: HS Jatana received his engineering education from BITS Pilani and had a brief stint at CMC Delhi as Software engineer wherein he worked on Railway Computerization Project, and later joined SCL in the CMOS division.
    He worked at Rockwell Semiconductor, California, USA where he was involved in design of R65 series of devices. He has worked in different areas of CMOS and has vast experience on CMOS design, Device testing / characterization, Test program development on ATE, Silicon debugging, and process Integration / porting over few technology nodes; starting from 5µm to sub-micron nodes. He also worked at AMS Austria for ten months on deputation for porting of SCL's CMOS processes at their foundry. Presently, as Group Head at SCL / ISRO is managing key divisions: VLSI Design, Process Development, Electro-optics devices.
    He has been instrumental in design of various ASICs and products viz, Energy meter chip, Single chip telephone, 12-bit ADC, 14-bit DAC, CMOS Imaging Sensor CIS, signal processor, SRAM, LVR, LDO's, RAdHARD devices etc. His areas of interest are low power CMOS design, analog design in DSM regime, process enhancements / optimization in DSM era. Has initiated many new process development modules like HV, SOI, BiCMOS, CCD process technology with back thinning, III-V materials on Si for photonics etc and APS for camera application, ultra-low power circuits (bias of few nA), rail-to-rail OTAs, RHDB SRAM etc.
    Also interested in spreading VLSI education and have delivered numerous lectures and tutorials on VLSI Design & Process Technology at ISRO centres, VECC (Dept of atomic energy), IISc Bangalore, IITs (Kharagpur, Madras, Bombay, Roorkee, Guwahati, Ropar), NITs (Hamirpur, Kurushetra, Manipur, Jaipur), NITTR Chandigarh, Assam State Technical university, Andhra University, Bangalore University, Panjab University, UIET-PU Chandigarh etc. He has also conducted a one-day tutorial at "17th VLSI Design and Test conference" (VDAT2015) and the "18th Conference" (VDAT2016). He is also conducting 'CMOS Analog Design' course for MTech students at IIST (Indian Institute of Space Technology) Trivandrum).
    He along with Dr GD Puri Head – Anaesthesia and Intensive care PGI Chandigarh has two patents to his credit for development of CLADS (Closed Loop Anaesthesia Drug Delivery System), which is being used on-line for critical surgeries like cardio vascular thoracic surgery.



    A Seminar on
    From Power Management to Energetic Intelligence: An evolutionary challenge for students, educators and designers
    Organized by: IEEE CAS Bangalore Chapter in cooperation with PragaTI (TI India Technical University)
    Speaker: Nicola Femia (University of Salerno, Italy)
    Date: 10 April, 2017
    Time: 11:00 AM to 12:00 PM
    Venue: Texas Instruments India, Bagmane Techpark, CV Raman Nagar, Bangalore 93

    Registration: This seminar is open to IEEE members and non-members. There is no registration fee to attend this seminar. Please write to khaja.smd@ti.com to enroll. Your participation will be confirmed by April 7 and further details will be sent.

    Abstract: Power Management Circuits and Systems provide electrical energy to all the objects making our life more comfortable, safer and funnier, like smart phones and watches, aircraft and automobiles, implanted prostheses and magnetic resonance machines, blenders and microwave ovens, robots and drones, digital TV sets and personal computers. The Design of Power Management Circuits and Systems is an exciting intellectual dare for students and educators, as it stimulates insight of interdisciplinary knowledge, understanding of new technologies, exploration of unconventional design solutions, discovery of the power of mathematics, reinforcement of problem solving capability, intelligent use of the energy and ultimately preservation of the environment and of the Earth's resources.
    Power Management Circuits and Systems have today to implement much more enhanced energy processing functions than in the past, thus bridging power designers into the era of Energetic Intelligence. University education and industry training has to coherently enhance, to proactively drive this evolution and to guide talented students and designers towards the achievement of powerful professional skills. The seminar intends to overview power management design issues and to propose a vision of the knowledge and tools needed to win the challenges of Energetic Intelligence.

    Nicola FemiaAbout the speaker: Nicola Femia is Full Professor at the University of Salerno, Italy, where he teaches Power Electronics and Energetic Intelligence. His research activities encompass circuit theory and applications, design and optimization of switching power supplies, magnetic power components modeling and optimization, power electronics and control techniques for photovoltaic systems, wireless power transfer systems. He has co-authored more than 150 technical papers on power electronics topics and five patents on photovoltaic control techniques. He leads the Power Electronics and Renewable Sources Laboratory of the Computer and Electrical Engineering and Applied Mathematics Department of the University of Salerno.
    He has directed many research projects in collaboration with worldwide leader companies, including Texas Instruments, National Semiconductor, Power-One/ABB, On Semiconductor, Whirlpool, STMicroelectronics, Coilcraft. Since 2001 he has delivered industry Power Electronics Design and Optimization courses and seminars, in Europe and United States, in collaboration with National Semiconductor, Texas Instruments, Silica/AVNET, Coilcraft. In 2014 he has been Visiting Professor in the Electrical Engineering (EE) Department of the Stanford University, Stanford, CA, where he taught Power Electronics Control and Energy Aware Design in the EE Enhanced Master Program. He is author and co-creator of the Texas Instruments Power Management Laboratory Kit (TI-PMLK).


    March
    A One-day Course on Analog System Design
    Organized by: IEEE-CAS Society, Bangalore Chapter in cooperation with Texas Instruments India
    We thank Chitkara University (Punjab and Himachal Pradesh) for supporting this event.
    Speaker: Dr. K.Radhakrishna Rao (TI India), Co-faculty: Sagar Juneja (Chitkara Univ.)
    Date: March 18, 2017
    Time: 9.00 AM - 5.00 PM
    Venue: Texas Instruments India, Bangalore Campus, Bangalore 560093

    Registration: This hands-on course intended for college teachers and student members of IEEE only.
    A course fee of Rs 500/- per person will be applicable, which will cover lunch and coffee.
    Write to secretary@ieee-cas-bangalore.org (with a copy to registration@ieee-cas-bangalore.org) with the following details before February 28, 2017.

      1. Full name of participant
      2. Status: Student/Faculty
      3. College:
      4. College ID is valid up to:
      5. IEEE membership number:
      6. IEEE membership valid up to:
    The fee needs to be paid to "IEEE CAS Bangalore Chapter" before March 5, 2017 by DD or Cheque. The DDs/Cheques can be sent to:
    C.P. Ravikumar, Secretary, IEEE CAS Bangalore Chapter, Texas Instruments, Bagmane Tec Park, CV Raman Nagar, Bangalore 560093

    NOTE:
    - If your registration is confirmed, you must pay the fee by March 10 (instructions will be sent).
    - If the payment is not received by March 10, your registration will not be confirmed.

    Abstract: Analog design has become a key part of modern SoC. Even embedded microcontrollers include some analog IP such as operational amplifiers, ADC, DAC, power regulators, oscillators, etc. In this 1-day course, the participants will get a hands-on introduction to analog system design. The course will include lectures as well as hands-on exercises. Participation certificates will be issued to participants at the end of the day.
    This program is intended only for teachers and students who are members of IEEE. The participants must have taken a course on linear integrated circuits/analog circuits.

    About the speakers:
    Dr.K Radhakrishna Rao is with Texas Instruments for the past 10 years as a part of the talent development team. Prior to joining TI, he spent over 30 years at IIT Madras as part of the faculty of Electrical Engineering Department.
    He has published numerous papers in the area of pure analog design. He has taught a number of courses related to analog design both at IIT Madras and Texas Instruments. At TI, he helped design the Analog System Lab Kit and coauthored the "Analog System Lab Manual" which are popularly used in engineering colleges across the world. He has recorded several popular video courses for NPTEL in the area of analog circuit design.


    Sagar Juneja is currently a Research Associate at Chitkara University Research & Innovation Network (CURIN), Chitkara University, Himachal Pradesh.


    February
    A Two-day Workshop entitled Science Editathon
    Organized by: IEEE-CAS Bangalore Chapter, In cooperation with Wikipedia Foundation and Texas Instruments, India
    Date: 4-5 February, 2017
    Time: 9.00AM to 5.00PM
    Venue: Texas Instruments India, Bangalore Campus

    Registration: The workshop is open to all IEEE members. Please register by writing to khaja.smd@ti.com. Your participation will be confirmed and further instructions will be mailed to you. All participants are expected to add at least one science article to Wikipedia.

    Abstract: Wikipedia is a great source of information in the 21st century. The intent of this workshop is to educate participants on how to edit Wikipedia articles on science-related topics.
    On Day-1, those who do not have Wikipedia accounts will create one for themselves and will be given an overview of how to add articles into Wikipedia and edit articles added by others. Best practices of writing and editing will be shared. In particular, the goal of this workshop is to add articles in Indian languages such as Kannada.


    January
    A Seminar on Authentication and Functional Obfuscation of Integrated Circuits
    Organized by: PragaTI (TI India Technical University) In cooperation with IEEE CAS Society, Bangalore Chapter
    Speaker: Prof. Keshab K. Parhi (Dept of ECE, University of Minnesota, Minneapolis)
    Date: January 13, 2017
    Time: 2:00 PM to 3:00 PM
    Venue: LC-2, TI India BTP Office, Bagmane Tech Park, CV Raman Nagar, Bangalore 560093

    Registration: This seminar is open to members of IEEE. Please call 080-25099727 and leave a message to confirm your participation. Please bring a photo-id to gain entrance. Limited parking is available for visitors.

    Abstract: The talk will focus on the important aspect of hardware security. Prof. Parhi will discuss the recent results that his team has unearthed in this area in two parts.
    Physical unclonable functions (PUFs) are small circuits that can exploit manufacturing process variations to generate unique signatures of chips. These unique signatures, in the form of challenge-response pairs, can be stored in a server and can be used to authenticate devices. Various delay-based PUFs include multiplexer (MUX) PUF and ring-oscillator PUF. Examples of memory PUFs include SRAM PUF and DRAM PUF. The speaker will talk about modeling both linear and nonlinear MUX PUFs, and will show that both hard and soft responses of linear and nonlinear MUX PUFs can be modeled by artificial neural network.
    The second part of the talk will be about functional obfuscation where the functionality is hidden by incorporating keys to a design such that the circuit only functions correctly if the key is correct. Various modes are introduced such that only the correct key triggers the correct functionality of the chip. One goal is to prevent foundries from manufacturing excess parts and selling in black market, Another goal is to prevent theft of intellectual property. A third goal of obfuscation is to prevent reverse engineering. The speaker will introduce the notions of fixed and dynamic obfuscation. We will show that the time to find the key by trial and error can be increased exponentially with dynamic obfuscation.

    Prof. Keshab K. ParhiAbout the speaker: Keshab K. Parhireceived the B.Tech. degree from the Indian Institute of Technology (IIT), Kharagpur, in 1982, the M.S.E.E. degree from the University of Pennsylvania, Philadelphia, in 1984, and the Ph.D. degree from the University of California, Berkeley, in 1988. He has been with the University of Minnesota, Minneapolis, since 1988, where he is currently Distinguished McKnight University Professor and Edgar F. Johnson Professor in the Department of Electrical and Computer Engineering.
    He has published 600 papers, is the inventor of 29 patents, and has authored the textbook VLSI Digital Signal Processing Systems (Wiley, 1999) and coedited the reference book Digital Signal Processing for Multimedia Systems (Marcel Dekker, 1999). Dr. Parhi is widely recognized for his work on high-level transformations of iterative data-flow computations, for developing a formal theory of computing for design of digital signal processing systems, and for his contributions to multi-gigabit Ethernet systems on copper and fiber and for backplanes.
    His current research addresses VLSI architecture design of signal processing, communications and biomedical systems, error control coders and cryptography architectures, high-speed transceivers, stochastic computing, hardware security, and molecular computing. He is also currently working on intelligent classification of biomedical signals and images, for applications such as seizure prediction and detection, schizophrenia classification, biomarkers for mental disorders, brain connectivity, and diabetic retinopathy screening.
    Dr. Parhi is the recipient of numerous awards including the 2012 Charles A. Desoer Technical Achievement award from the IEEE Circuits and Systems Society, the 2004 F. E. Terman award from the American Society of Engineering Education, the 2003 IEEE Kiyo Tomiyasu Technical Field Award, the 2001 IEEE W. R. G. Baker prize paper award, and a Golden Jubilee medal from the IEEE Circuits and Systems Society in 2000. He is a Fellow of IEEE (1996). He served as the Editor-in-Chief of the IEEE Trans. Circuits and Systems, Part I during 2004-2005, and as an elected member of the Board of Governors of the IEEE Circuits and Systems society from 2005 to 2007.
    For more information on the speaker, visit http://www.ece.umn.edu/~parhi


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