IEEE - CAS Bangalore Chapter, India     CAS Chapter - Region 10
Institute of Electrical and Electronics Engineers - Circuits and Systems Society
Goals: To conduct seminars, workshops, and other events pertaining to all aspects of electronic circuits and systems

Events - 2018
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November
The Seventh Edition of PES University's Open Hackathon on #CODE 2K18
Presented by: Microsoft Innovation Lab and Sponsored by IEEE CAS Bangalore Chapter and Amper AXP
Date: November 3-4, 2018
Venue: MRD Auditorum, PES University, Bangalore

Click here for full event details

September
Technical Session on
Mixed Signal Design and Compact Modeling and the Launch of CFP of IEEE MOS AK India 2019
Organized by: IEEE Bangalore Section, IEEE Bangalore Chapter and IEEE CAS/EDS Hyderabad Section In collaboration with Swissnex India (Connecting Dots between Switzerland and India)
Speakers: Dr. P.V. Ananda Mohan (Fellow IEEE) and Dr. Santanu Mahapatra (IISc Bangalore)
Date: 14 September 2018
Time: 4.30 PM to 6.00 PM
Venue: Seminar Hall, 26 Rest House Crescent Road, Bangalore 560001

Click here for full event details
Download program details (PDF)


Seminar on Advanced Biometric Technologies
Organized by: IEEE CAS Bangalore Chapter in association with IEEE Bangalore Section and Texas Instruments
Speaker: Prof. Vincenzo Piuri (Department of Computer Science, Universiti degli Studi di Milano)
Date: 20 September 2018
Time: 11.00am - 12.00 noon
Venue: Texas Instruments India, Bagmane Techpark, C.V.Raman Nagar Bangalore Campus, 560093

Click here for full event details



IEEE WINTECHCON - 2018: Women's Technical Conference
Objective: To provide opportunities to women technology leaders from India to present their work in emerging knowledge areas
Theme: Designing the Future Electronic Systems & Applications

For full details of the conference and updates, click here
Update: 19 September 2018
Download Advance Technical Program (PDF)
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Download FAQ on Paper & Demo Submissions (PDF)
Download Call for Participation (PDF)
Download Women in Technology – A conference with a difference (Blog - PDF)
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IEEE WINTECHCON - 2018

Organized by: IEEE CAS Bangalore Chapter; In cooperation with IEEE Bangalore Section and IEEE WiE Council (IEEE Women in Engineering), Bangalore
Date: 28 September 2018 (Friday)
Time: 9.00 AM - 5.00 PM
Venue: HOTEL ROYAL ORCHID
#1, Golf Avenue, Adjoining KGA Golf Course, HAL Airport Road, Bengaluru Karnataka India-560008

    

WINTECHCON - 2018 Participants

Sponsorship Opportunity: Companies that wish to sponsor the conference may contact Antaash Sheikh (Antaash@ti.com).
For Sponsorship form, please write to Antaash@ti.com or wintechcon@ieee-cas-bangalore.org

Registration: The conference is open to all to attend. IEEE/IEEE-CAS/IEEE WiE members can avail discounted rates.

  + Preliminary Registration: (Not compulsory - Click for details)

(Click for details. If the browser is not Java enabled and the details are not displayed, download CFP)

Paper Submission:
Paper submissions are now closed.
Submitting authors will be notified about the status of their submissions by end of August.

Submission Guidelines:


Download FAQ on Paper & Demo Submissions (PDF)

STEP 1 STEP 2 STEP 3
Regular paper submission Demo projects
  • If you wish to submit a proposal for a DEMO, you must submit a set of foils in the format specified below. Convert your Power Point foils to PDF and upload before July 29 (final extension).
  • PPT Template can be Downloaded here (Right-click/Save As).
  • OR Download PPT Template as a Zip file.
Please note:
  • The principal author and the presenter of the paper must be a woman engineer.
  • File size should not exceed 5MB.
  • All the coauthors must be shown in the initial submission. No further authors can be added for selected papers.
  • Submissions close on 22 July 2018 (final extension), and all authors will be notified on the status of acceptance.
  • Final submissions for the selected papers will be activated with notification.

Call for Papers:

  • Women professionals from technology industries (semiconductor/hardware/software) and women teachers/students from engineering colleges may submit papers.
  • The principal author and the presenter of the paper must be a woman engineer.
  • It is mandatory to adhere to the theme.
  • Each paper must be at most 6 pages in length, in IEEE conference format, including figures and tables. The papers will be reviewed by a committee and authors of selected papers will be invited to present their papers. In addition to papers, there will be provision to demonstrate software/hardware projects developed by women. Projects that address humanitarian issues and women's issues through technology are also welcome.
  • High-quality manuscripts that describe work carried out by the authors in the areas of the conference mentioned below may be submitted no later than July 29 (final extension).
  • Please do not submit survey papers or tutorials.
  • The manuscript must be submitted in PDF format and must be set in IEEE Conference format and must be within a limit of 6 A4 sheets in double column format and 10-point.
  • Templates may be downloaded from: https://www.ieee.org/conferences/publishing/templates.html

NOTE:
  • The primary author of the paper must be a woman.
  • If a manuscript is accepted for presentation, the authors will be expected to also submit a final version of the manuscript as well as a set of foils that will be presented at the conference.
  • The presenting author of the paper must also be a woman.
  • The papers and foils will be made available to all attendees of the conference and will also receive high visibility through IEEE CAS Bangalore.

Areas of the conference: The conference will deal with design, IP, verification, test, software and systems aspects of the following areas. Papers and project demos are being sought in each of these areas.

  • IoT: Industrial, Medical and Wearables
  • Automotive : Radar, Safety, HEV
  • Smart Energy
  • Computing - Hyperscale, Cloud, Cognitive, Mobile edge, Quantum
  • Artificial Intelligence and Data Analytics
  • Personal Electronics

Steering Committee:

Contact: wintechcon@ieee-cas-bangalore.org

  • Roopashree H.M., Texas Instruments (Chair)
  • C.P. Ravikumar, Texas Instruments (Advisor)
  • Viji Ranganna, Qualcomm
  • Rituparna Mandal, Media Tek
  • Sumedha Limaye, Intel
  • Jaya Singh, Texas Instruments
  • Parvathi Rachakonda, IBM

Technical Committee:

  • Rittu Sachdev, Texas Instruments
  • Neha Vernekar, Texas Instruments
  • Juby Jose, Intel
  • Ranjini M, Texas Instruments
  • Anjana Ghosh, Canon
  • Dr. Seema Chopra, Boeing
  • Chaitra M Bhat, IBM
  • Divya K Konoor, IBM
  • Mousumi Baruah, Bosch
  • Sunitha Cherkottu, Texas Instruments
  • Mithula Madiraju, IBM
  • Garima Srivastava, Samsung
  • Krishna Paul, Intel
  • Jiji Jayadevan, Mediatek
  • Raka Singh, Analog Devices
  • Deepti Varadarajan, Mediatek

Organizing Committee:

  • Mitu Misha, Texas Instruments
  • Suhasini Singh, Texas Instruments
  • Antaash Sheikh, Texas Instruments
  • Annapurna Patil, IEEE WiE, Bangalore
  • Deepa Shenoy, IEEE WiE Bangalore
  • Sidhartha Mohanty, Intel

Sponsorship:

  • Antaash Sheikh, Texas Instruments
  • Contact: Antaash@ti.com

Important Dates:

June 29Indicate interest in participation here
(extended from June 15)
Even those initially not registered can submit or attend
July 29Deadline for submission of papers
(final extension: extended from July 22)
July 9Online Registration begins
(advanced from Aug 1)
Aug 28Communication to authors
Sep 15Deadline for registration
Sep 28Conference



July
Seminar on Disciplined Entrepreneurship: The Framework for Innovation Driven Ventures
Organized by: PragaTI (TI India Technical University) in cooperation with IEEE-CAS Bangalore Chapter
Speaker: Nidhi Sharma (MIT)
Date: 27 July 2018
Time: 11.00 AM to 12.00 PM
Venue: Texas Instruments, Bagmane Tech Park, CV Raman Nagar, Bangalore 560093
Click here for full event details


Workshop on Using Software Development Kits and Plug-ins for Seamlessly Prototyping IoT based end applications
Organized by: IEEE CAS Bangalore Chapter and Supported by IEEE Bangalore Section
Instructors: Osheen Nayak and Manoj R. (Texas Instruments India)
Date: 28 July 2018
Time: 9.00AM to 1.00PM
Venue: Texas Instruments India, Bagmane Techpark, C.V.Raman Nagar Bangalore Campus, 560093

Abstract: There is widespread interest in the space of IoT (Internet of Things) and new applications are being announced each day. Yet, the development of software for an IoT application presents a number of challenges to the developers. Since IoT is interdisciplinary, it is not uncommon to see professionals from multiple disciplines such as mechanical, civil, electrical, electronics and computer engineering to work on IoT projects. As a result, the software development platform must be easy to use. This workshop will enable the participants to learn about using software development kits along with plug-ins to make the prototyping a seamless process. It is a platform for the participants to understand and create ready-to-use IoT-based end-applications.

Intended Audience:
Students and hobbyists coming from electronics, mechanical or computer science background and any professional working with Internet of Things based end applications.

Download Workshop agenda (PDF) for the Session structure with Pre-Work, Course Description and FAQ on the nature of course with registration details.

About the instructors:
Manoj R
Manoj is a Senior Software Engineer at TI and holds his expertise in the domain of functional safety, Software Development Kits and Plugins for IoT based devices. He has been working with TI since 2011 and holds a Master's degree in Embedded Systems from BITS Pilani.
Manoj is a seasoned presenter and blogger and has presented in various conferences like IEEE INIS, VDA Automotive SYS Conference, while his blogs are published on embedded.com. Manoj has regularly delivered talks at various institutes in Karnataka consistently.
His hobbies are playing badminton and cricket, along with cycling at weekends.

Osheen Nayak
Osheen is a Software Engineer at TI and is experienced in SDKs and plugins for IoT based devices. His other areas of interests and expertise include Natural Language Processing, Computer Vision, Data Science and machine learning.
Osheen has been with TI for 12 months and his alma mater is Delhi Technological University, from where he completed his Bachelor's degree in "Engineering Physics with Majors in Electronics". Osheen has delivered seminars and tech talks for IEEE and TI on "A primer on Machine Learning and Artificial Intelligence" and "Natural Language Processing".

Registration: The seminar is open to both IEEE/CAS members snd non-members.
Registration fee:

  • For IEEE Members: Rs 500/-
  • For Non-members: Rs 750/-

  • Registration fees includes working lunch and a participation certificate. Upto 30 seats are available. Prior registration is compulsory. Register online no later than July 15, preferably with payment details to indicate positively attending the event. Your registration will be confirmed and further details will be mailed.

    + Payment Instructions
    (Click for details. If the browser is not Java enabled and the details are not displayed, download Workshop agenda)


    June

    IEEE-CAS Bangalore Chapter is organizing 2-DIY events: One-day conference IDIYE 2018 on June 16, 2018 and a Two-day Electronics DIY - A Hands-on Approach during June 17-18, 2018. Both the events require separate registrations. Please refer to the details below.


    1. IDIYE 2018
    One-day Conference on INNOVATION & DO-IT-YOURSELF ELECTRONICS
    Organized by: IEEE CAS Bangalore Chapter and Supported by IEEE Bangalore Section & Texas Instruments India
    Conference General Chair: C.P.Ravikumar (Texas Instruments India)
    Date: 16 June 2018
    Time: 9.00 AM - 5.00 PM
    Venue: Texas Instruments India, Bagmane Techpark, C.V.Raman Nagar Bangalore Campus, 560093

    Update
    REPORT ... PHOTOS ... Download PROCEEDINGS (Zip 27MB Right-click/Save As)

    Download Advance Program (PDF)

    Program highlights:
    Keynote Talk:
    N.Kavitha (STEPS Knowledge Services Pvt Ltd, Coimbatore)

    Panel discussion:
    DIY Electronics – What will take us to the next level?

    Moderator: C.P. Ravikumar
    How can DIY projects from India be more innovative and relevant to India?
    N.Kavitha (STEPS Knowledge Services Pvt Ltd, Coimbatore)
    Is the curriculum driving students towards or away from Electronics DIY?
    Prof.Dhananjay V. Gadre (CEDT, NSIT Delhi)
    Are Governmental initiatives helping in expanding DIY?
    Navratan Katariya (Director-Startups with the Govt. funded NASSCOM)

    Paper presentations
    Project demo and Poster Presentation by authors

    IDIYE-2018Registration: Register online no later than May 25, 2018 and make the payment either through NEFT or by sending a DD/Chq using the below details. The DD/Chq should reach us by June 2, 2018. Fee will include a working lunch and refreshments and a participation certificate.
    Authors can submit their work at https://www.surveymonkey.com/r/6M7HL6K till May 15.

    For NEFT:
    Name of the account / Payable to: IEEE CAS Bangalore Chapter
    A/C number – 1057 2947 24
    Central Bank of India
    Miller Road Extension Branch (Code 02314)
    IFSC Code: CBIN0282314

  • NOTE: Please send a screenshot of the NEFT Transaction to accounts@ieee-cas-bangalore.org with a copy to registration@ieee-cas-bangalore.org mentioning your Name and A/c number for our reference.
  • .
    Your registration will be confirmed and further details will be mailed.

    For DD/Chq payments:
  • Prepare the DD (Demand Draft) or cheque for the amount to "IEEE CAS Bangalore Chapter" payable at Bangalore. The DD is to be sent to: "C.P. Ravikumar, Secretary, IEEE CAS Bangalore Chapter, Texas Instruments, Bagmane Tech Park, CV Raman Nagar, Bangalore 560093" to reach us by June 2, 2018.
  • Please write your Name and Phone number on the reverse side of DD/Chq for our reference.
  • Send the scanned copy of the DD/Chq through mail to accounts@ieee-cas-bangalore.org with a copy to registration@ieee-cas-bangalore.org as a safeguard, considering postal delay or any loss during transit.
  • Registration fee structure for IDIYE 2018
    Category Students and Teachers Professionals
    IEEE Members
    (you must provide proof of membership)
    Rs 500/- (Before May 15)
    Rs 750/- (After May 15)
    Rs 1000/- (Before May 15)
    Rs 1500/- (After May 15)
    IEEE Non-Members Rs 750/- (Before May 15)
    Rs 1000/- (After May 15)
    Rs 1500/- (Before May 15)
    Rs 2000/- (After May 15)

    Payments sent via post must be received by June 5 at the most.
    Cancellation Policy: Cancellation must be made on or before June 2. Cancellations made before June 2 will result in a processing fee of Rs 500/-. Cancellations made after June 2 will incur a cancellation and processing fee of Rs 750/-.

    Abstract: The goal of IDIYE 2018 is to provide a platform to electronics DIYers who believe in innovation at the system-level to showcase their DIY projects. This conference is open to all IEEE members who may be students, faculty members, and working professionals.

    • The topic of the conference concerns innovative electronic system design. It does not include chip design.
    • Accepted papers must be presented and the projects must be demonstrated (Venue will be TI office).
    • Certificates from IEEE will be provided to authors of all accepted papers.
    • The authors are expected to submit PPT foils describing their projects before May 15.
    • Please ensure that your submission does not contain any proprietary information.
    • Title Slide with Project title, names of authors and their affiliations.
    • Problem Description – 1 slide that brings out the (societal) problem that your project addresses. This slide should bring out the importance of your work.
    • Related Work and their limitations – 1 slide that shows the limitations of existing solutions (e.g. cost/power/performance etc.).
    • Innovation – Up to 5 slides that show your design and innovation.
    • Overall Contribution – 1 slide that shows where your work stands today, and how it is making/can make a difference.
    • References – 1 slide with references to papers/past DIY projects.

    Important Dates: Please fill out the following form before April 30 to indicate your intent in submitting your work to this conference:
    https://www.surveymonkey.com/r/6M7HL6K

    History: The first IDIYE event was held in 2017 and was a big success. Visit: IDIYE 2017



    2. Two-day workshop on Electronics DIY - A Hands-on Approach
    Organized by: IEEE CAS Bangalore Chapter and Supported by IEEE Bangalore Section & Texas Instruments India
    Instructor: Prof. Dhananjay V. Gadre (NSIT, New Delhi, India)
    Date: June 17-18, 2018
    Time: 9 AM to 5 PM
    Venue: Texas Instruments India, Bagmane Techpark, C.V.Raman Nagar Bangalore Campus, 560093

    Download workshop announcement with workshop agenda (PDF)

    Registration: The workshop is open to both IEEE and non-members. There is a nominal fee to cover the costs of the workshop. Participants will get a working lunch and refreshments on the days, a certificate, and an MSP430 LunchBox. Register online no later than May 25, 2018 and make the payment either through NEFT or by sending a DD using the below details. The DD/Chq should reach us by June 2, 2018:
    For NEFT:

    Name of the account / Payable to: IEEE CAS Bangalore Chapter
    A/C number – 1057 2947 24
    Central Bank of India
    Miller Road Extension Branch (Code 02314)
    IFSC Code: CBIN0282314
  • NOTE: Please send a screenshot of the NEFT Transaction to accounts@ieee-cas-bangalore.org with a copy to registration@ieee-cas-bangalore.org mentioning your Name and A/c number for our reference.
  • .
    Your registration will be confirmed and further details will be mailed.
    For DD/Chq payments:
  • Prepare the DD (Demand Draft) or cheque for the amount to "IEEE CAS Bangalore Chapter" payable at Bangalore. The DD is to be sent to: "C.P. Ravikumar, Secretary, IEEE CAS Bangalore Chapter, Texas Instruments, Bagmane Tech Park, CV Raman Nagar, Bangalore 560093" to reach us by June 2, 2018.
  • Please write your Name and Phone number on the reverse side of DD/Chq for our reference.
  • Send the scanned copy of the DD/Chq through mail to accounts@ieee-cas-bangalore.org with a copy to registration@ieee-cas-bangalore.org as a safeguard, considering postal delay or any loss during transit.
  • Registration fee structure for Electronics DIY
    There are a limited number of seats. Priority will be given to members of IEEE.
    Category Students and Teachers Professionals
    IEEE Members
    (you must provide proof of membership)
    Rs 3000/- Rs 4000/-
    IEEE Non-Members Rs 4000/- Rs 5000/-

    Payments sent via through post must be received by June 5 at the most.
    Cancellation Policy: Cancellation must be made on or before June 2. Cancellations made before June 2 will result in a processing fee of Rs 500/-. Cancellations made after June 2 will incur a cancellation and processing fee of Rs 750/-.

    EDIY 2018Abstract: Are you interested in Electronics DIY projects? Do you have dreams of designing great products? All journeys begin with the first step. Attending this two-day workshop will launch you into the world of DIY, embedded processors, hardware, and embedded software.
    Prof. Dhananjay Gadre, a well-known DIY-er and an experienced teacher who has trained a large number of DIY-ers, will guide you through the process of doing an electronics project. Learn about what are some best practices, what are some false starts, what are good and bad ideas. Also learn how to get started with a microcontroller-based project with a low-cost product called the MSP430 LunchBox. Incidentally, the "LunchBox" was a DIY project that was conceived and developed under the mentorship of Prof. Gadre.
    More than 50 experiments and small projects can be performed using the LunchBox when it is used with the Mini Voyager-1 system, which is also a product from Prof. Gadre's lab.
    About LunchBox and Mini-Voyager-1
    https://dvgadre.blogspot.in/2018/05/a-diy-ecosystem-for-learning.html

    Each participant will receive an MSP430 LunchBox and a Mini-Launcher-1 to keep!

    Who should attend?: The workshop is ideal for undergraduate students and postgraduate students, teachers from engineering colleges and working professionals who wish to dabble in DIY. It is expected that the students have taken a course on digital and analog electronics and are familiar with C programming and Internet tools. You should be a DIY person and must be willing to help yourself. There are a limited number of seats. Priority will be given to members of IEEE.

    Prof. Dhananjay V. GadreAbout the Instructor: Prof. Dhananjay V. Gadre (NSIT, New Delhi, India) is an avid DIY-er, a passionate teacher, and a renowned author completed his MSc (electronic science) from the University of Delhi and M.Engr (computer engineering) from the University of Idaho, USA. In his professional career of more than 28 years, he has taught at the SGTB Khalsa College, University of Delhi, worked as a scientific officer at the Inter University Centre for Astronomy and Astrophysics (IUCAA), Pune, and since 2001, has been with the Electronics and Communication Engineering Division, Netaji Subhas Institute of Technology (NSIT), New Delhi, currently as an associate professor. He directs two open access laboratories at NSIT, namely Centre for Electronics Design and Technology (CEDT) and TI Centre for Embedded Product Design (TI-CEPD).

    Professor Gadre is the author of several professional articles and six books. One of his books has been translated into Chinese and another one into Greek. His recent book "TinyAVR Microcontroller Projects for the Evil Genius", published by McGraw Hill International consists of more than 30 hands-on projects and has been translated into Chinese and Russian. His latest book on TIVA ARM Cortex M4 microcontrollers published by Springer is just hot off the press! He is a licensed radio amateur with a call sign VU2NOX and hopes to design and build an amateur radio satellite in the near future.




    IEEE Bangalore Section holds a workshop to help members aspiring for Senior Grade Elevation
    Organized by: IEEE CAS Bangalore Chapter and IEEE Bangalore Section
    Speakers: Puneet Mishra (Vice Chair, IEEE Bangalore Section), Keshav Bapat (Chair-Elect, IEEE Bangalore Section), Dr.Chetan Thakur (Electonic Systems Engineering, IISc Bangalore) and Manav Mediratta (Texas Instruments, India)
    Date: 9 June 2018
    Venue: Texas Instruments India, Bangalore Campus, Bagmane Techpark, CV Raman Nagar 560093

    Report ... Photos

    Intent: The workshop is aimed to facilitate IEEE members who are aspiring to get elevated to senior grade membership. IEEE offers memberships of different types, starting with student membership, moving on to professional membership, senior membership, fellow membership, and life membership. Senior membership is offered to a very small number of members who have done noteworthy work in their chosen fields.





    One-day hands-on tutorial on Problem Solving with Python
    Organized by: IEEE-CAS Bangalore Chapter
    Instructor: Dr. C.P. Ravikumar (Texas Instruments India)
    Date: 2 June 2018
    Time: 9.00 AM to 5.00 PM
    Venue: Texas Instruments India, Bangalore Campus, Bagmane Techpark, CV Raman Nagar 560093

    Registration: Participants must register online and make the payment either through NEFT or by sending a cheque using the below details no later than May 26. NOTE: Only 10 seats are available, and will be prioritized for early registrations.
    For NEFT:

    Name of the account / Payable to: IEEE CAS Bangalore Chapter
    A/C number – 1057 2947 24
    Central Bank of India
    Miller Road Extension Branch (Code 02314)
    IFSC Code: CBIN0282314
  • NOTE: Please send a screenshot of the NEFT Transaction to accounts@ieee-cas-bangalore.org with a copy to registration@ieee-cas-bangalore.org mentioning your Name and A/c number for our reference.

  • Course fees
    IEEE Student Members Faculty with IEEE Membership Non-members Students/Faculty IEEE Members (Professional) Non-Members (Professional)
    Rs 500/- Rs 750/- Rs 1000/- Rs 2000/- Rs 3000/-

    For DD/Chq payments:
  • Prepare the DD (Demand Draft) or cheque for the amount to "IEEE CAS Bangalore Chapter" payable at Bangalore. The DD is to be sent to: "C.P. Ravikumar, Secretary, IEEE CAS Bangalore Chapter, Texas Instruments, Bagmane Tech Park, CV Raman Nagar, Bangalore 560093" to reach us atmost by May 28.
  • Please write your Name and Phone number on the reverse side of DD/Chq for our reference.
  • Send the scanned copy of the DD/Chq through mail to accounts@ieee-cas-bangalore.org with a copy to registration@ieee-cas-bangalore.org as a safeguard, considering postal delay or any loss during transit

  • Please register online no later than May 26. Your registration will be confirmed and further details will be mailed.
    Payment must be received by May 28 at the most. Confirmation and further instructions will be sent to participants who complete this process.


    Cancellation Policy: Cancellation must be made on or before May 26. Cancellations made before May 26 will result in a processing fee of Rs 500/-. Cancellations made after May 26 will incur a cancellation and processing fee of Rs 750/-.
    Fee will include a working lunch and refreshments and a participation certificate.

    Abstract: Python is a general-purpose programming language which allows rapid software prototyping. When compared to C, Python programs require much fewer lines of code. The availability of a number of libraries for numerical and scientific computing in Python also makes it very attractive. In this course, we will provide an introduction to Python, assuming that the participant is familiar with either C, C++, or Perl. The course will use lectures, demo and hands-on exercises. The topics we will touch upon include:

      1. Importance of Python
      2. Fundamental datatypes such as scalar variables, tuples, lists, dictionaries in Python and operations on fundamental data types
      3. Control Structures, including subroutines and lambda functions
      4. Modules
      5. Command-line arguments
      6. File I/O
    We will consider examples from electronic circuits domain.

    Dr.C.P.Ravikumar (Texas Instruments India)About the Instructor: C.P. Ravikumar is presently the Director of Technical Talent Development at Texas Instruments, India. He leads the TI India Technical University which provides learning opportunities to employees of TI India. His earlier roles in TI include Director of University Relations and Senior Technologist (VLSI Test).  He is also an adjunct faculty at IIT Madras.  Before joining TI India in 2001, Ravikumar was a Professor of Electrical Engineering at the Indian Institute of Technology, Delhi (1991-2001). He also held a visiting position at the University of Southern California (1995-1996) and the position of Vice President (Training) atControlnet India Pvt Ltd (2000-2001).  He obtained his Ph.D. (Computer Engineering) from the University of Southern California (1991), M.E. in Computer Science with highest scores from Indian Institute of Science (1987) and B.E. in Electronics with a Gold Medal from Bangalore University (1983).
    He has published over 200 papers in leading International conferences and journals. He founded the VLSI Design and Test Symposium (VDAT) and was the General Chair of this event for 15 years, from its inception in 1998 to 2011. He is the author/editor/coauthor of over 12 books in areas of VLSI and has contributed several book chapters.  He is the editor of the Journal of VLSI and Electronic System Design and on the editorial board of the Journal of Electronic Testing – Theory and Applications and the Journal of Low Power Electronics. He has won the best paper award at IEEE International Conference on VLSI Design (2002) and VLSI Test Symposium (2005). He is a Senior Member of IEEE, honorary secretary of IEEE CAS Bangalore chapter (2004-current) which he founded, and the honorary secretary of VLSI Society of India (2003-2011).


    May
    Seminar on Variable speed drives
    Organized by: IEEE CAS Bangalore Chapter and IEEE Bangalore Section
    Speaker: Navaneeth Kumar N (MGTS, Systems manager - Motor drives, Texas Instruments Incorporated)
    Date: 31 May 2018
    Time: 3.00pm - 4.00pm
    Venue: Dept of Electrical Engineering, IISc, Bangalore

    Registration: The seminar is open to IEEE members and non-members. There is no fee to attend, but prior registration is needed. Register online no later than May 28. Your registration will be confirmed and further details will be mailed.

    Abstract: The talk is intended to provide a better perspective to the students on how OEM's design and what factors influence the architecture.
    Variable speed drives have been in the market for long and has been undergoing constant changes to meet up with the market requirements, IEC standards and technological advancements in power, computational devices, diagnostics and communication interfaces. This session will focus on Market trends, different power stage architecture (Current sensing, Gate driver and Isolation) used in drive, functional safety in drives, EMC standards and application of WBG devices in drives.

    Agenda:

    1. Introduction to Variable speed drives
    2. Market trends
    3. Isolation in power stage
    a. Choices to optimize protection, performance and cost
    b. Capacitive Isolation
    4. Current sensing
    a. Different techniques
    b. 2 or 3 sensors for motor control
    5. Functional safety in drives
    a. Safe torque off - example
    6. EMC standards and overview of tests
    7. Penetration of SiC in motor drives
    8. Open Discussion

    Navaneeth KumarAbout the speaker: Navaneeth Kumar N is MGTS, Systems manager - Motor drives at Texas Instruments Incorporated. More information on him can be viewed here.


    April
    Hands-on Introduction to Design and Verification through Verilog and System Verilog
    Jointly Organized by: IEEE Student Branch CEC Mangalore and IEEE CAS Bangalore Chapter
    Speaker: Dr. C.P. Ravikumar (Texas Instruments India)
    Date: 22 April 2018 (Sunday)
    Time: 9.00 AM to 5.00 PM
    Venue: Canara Engineering College, Mangalore
       

    Registration: The registration is open to all IEEE student members and faculty from engineering colleges. At most 30 participants will be permitted.
    Participants must register online.

    QR Code of Registration Form

    Conveyance: College Bus via a common route shall be arranged and registered participants will be notified.

    Queries:
    Prof. Vinay H S |+9199480026957|
    Prof. Naidile S | +918296320489|
    Amritha Shenoy |+919495177148|
    Vignesh Pai |+919481022756|

    For Details Please visit: canaraengineering.in ... Download announcement (PDF)

    Abstract: One of the most resource and time-intensive steps in the SoC Design Flow is the verification of the design. The participants of this workshop will get an introduction to the topic of digital design verification. In particular, Verilog and System Verilog will be discussed and RTL coding and development of test benches will be provided. The participant must have taken a class on Digital Design and must be familiar with combinational and sequential logic design. Prior exposure to VLSI Design and VHDL or Verilog will be useful. PCs will be available to participants for carrying out hands-on exercises. However you can get your own laptops with the necessary software as well.

    Dr.C.P.Ravikumar (Texas Instruments India)About the speaker: C.P. Ravikumar is presently the Director of Technical Talent Development at Texas Instruments, India. He leads the TI India Technical University which provides learning opportunities to employees of TI India. His earlier roles in TI include Director of University Relations and Senior Technologist (VLSI Test).  He is also an adjunct faculty at IIT Madras.  Before joining TI India in 2001, Ravikumar was a Professor of Electrical Engineering at the Indian Institute of Technology, Delhi (1991-2001). He also held a visiting position at the University of Southern California (1995-1996) and the position of Vice President (Training) atControlnet India Pvt Ltd (2000-2001).  He obtained his Ph.D. (Computer Engineering) from the University of Southern California (1991), M.E. in Computer Science with highest scores from Indian Institute of Science (1987) and B.E. in Electronics with a Gold Medal from Bangalore University (1983).
    He has published over 200 papers in leading International conferences and journals. He founded the VLSI Design and Test Symposium (VDAT) and was the General Chair of this event for 15 years, from its inception in 1998 to 2011. He is the author/editor/coauthor of over 12 books in areas of VLSI and has contributed several book chapters.  He is the editor of the Journal of VLSI and Electronic System Design and on the editorial board of the Journal of Electronic Testing – Theory and Applications and the Journal of Low Power Electronics. He has won the best paper award at IEEE International Conference on VLSI Design (2002) and VLSI Test Symposium (2005). He is a Senior Member of IEEE, honorary secretary of IEEE CAS Bangalore chapter (2004-current) which he founded, and the honorary secretary of VLSI Society of India (2003-2011).


    March
    Hands-on Introduction to Design and Verification through Verilog and System Verilog
    Organized by: IEEE CAS Bangalore Chapter and Supported by: Texas Instruments, India and IEEE Bangalore Section
    Speaker: Dr. C.P. Ravikumar (Texas Instruments India)
    Date: 24 March 2018 (Saturday)
    Time: 9.00 AM to 5.00 PM
    Venue: Texas Instruments India, Bangalore Campus, Bagmane Techpark, CV Raman Nagar

    Registration: Participants must register online and make the payment either through NEFT or by sending a cheque using the below details:
    For NEFT:

    Name of the account / Payable to: IEEE CAS Bangalore Chapter
    A/C number – 1057 2947 24
    Central Bank of India
    Miller Road Extension Branch (Code 02314)
    IFSC Code: CBIN0282314
  • NOTE: Please send a screenshot of the NEFT Transaction to accounts@ieee-cas-bangalore.org with a copy to registration@ieee-cas-bangalore.org mentioning your Name and A/c number for our reference.

  • Course fees
    IEEE Student Members Faculty with IEEE Membership Non-members Students/Faculty IEEE Members (Professional) Non-Members (Professional)
    Rs 500/- Rs 750/- Rs 1000/- Rs 2000/- Rs 3000/-

    For DD/Chq payments:
  • Prepare the DD (Demand Draft) or cheque for the amount to "IEEE CAS Bangalore Chapter" payable at Bangalore. The DD is to be sent to: "C.P. Ravikumar, Secretary, IEEE CAS Bangalore Chapter, Texas Instruments, Bagmane Tech Park, CV Raman Nagar, Bangalore 560093" to reach us by March 13.
  • Please write your Name and Phone number on the reverse side of DD/Chq for our reference.
  • Send the scanned copy of the DD/Chq through mail to accounts@ieee-cas-bangalore.org with a copy to registration@ieee-cas-bangalore.org as a safeguard, considering postal delay or any loss during transit

  • Please register online no later than March 10. Your registration will be confirmed and further details will be mailed.
    Payment must be received by March 13 at the most. Confirmation and further instructions will be sent to participants who complete this process.

    Cancellation Policy: Cancellation must be made on or before March 17. Cancellations made before March 17 will result in a processing fee of Rs 500/-. Cancellations made after March 17 will incur a cancellation and processing fee of Rs 750/-.
    Fee will include a working lunch and refreshments and a participation certificate.

    Abstract: In this one-day program targeted at students and faculty, the participants will get an introduction to the topic of digital design verification. In particular, we will discuss Verilog and System Verilog and provide examples of RTL coding and development of testbenches. The student must have taken a class on Digital Design and must be familiar with combinational and sequential logic design. Prior exposure to VLSI Design and VHDL or Verilog will be useful. PCs will be available to participants for carrying out hands-on exercises.

    Dr.C.P.Ravikumar (Texas Instruments India)About the speaker: C.P. Ravikumar is presently the Director of Technical Talent Development at Texas Instruments, India. He leads the TI India Technical University which provides learning opportunities to employees of TI India. His earlier roles in TI include Director of University Relations and Senior Technologist (VLSI Test).  He is also an adjunct faculty at IIT Madras.  Before joining TI India in 2001, Ravikumar was a Professor of Electrical Engineering at the Indian Institute of Technology, Delhi (1991-2001). He also held a visiting position at the University of Southern California (1995-1996) and the position of Vice President (Training) atControlnet India Pvt Ltd (2000-2001).  He obtained his Ph.D. (Computer Engineering) from the University of Southern California (1991), M.E. in Computer Science with highest scores from Indian Institute of Science (1987) and B.E. in Electronics with a Gold Medal from Bangalore University (1983).
    He has published over 200 papers in leading International conferences and journals. He founded the VLSI Design and Test Symposium (VDAT) and was the General Chair of this event for 15 years, from its inception in 1998 to 2011. He is the author/editor/coauthor of over 12 books in areas of VLSI and has contributed several book chapters.  He is the editor of the Journal of VLSI and Electronic System Design and on the editorial board of the Journal of Electronic Testing – Theory and Applications and the Journal of Low Power Electronics. He has won the best paper award at IEEE International Conference on VLSI Design (2002) and VLSI Test Symposium (2005). He is a Senior Member of IEEE, honorary secretary of IEEE CAS Bangalore chapter (2004-current) which he founded, and the honorary secretary of VLSI Society of India (2003-2011).



    Tutorial on Introduction to VLSI Design - An Industry Perspective
    Organized by: Department of Electronics and Communication Engineering, GSSS, Mysore, In cooperation with IEEE Circuits and Systems Society Bangalore Chapter
    Speaker: Dr. C.P.Ravikumar (Texas Instruments, India)
    Date: 3 March 2018
    Time: 10.00 AM to 4.00 PM
    Venue: GSSS Institute Of Engineering And Technology For Women, Mysore

    Registration: Please contact: Rohini Nagapadma (rohini_nagapadma@yahoo.co.in) with a copy to registration@ieee-cas-bangalore.org

    Abstract: In this tutorial, we will provide an overview of modern-day system-on-chip design. The design flow will be discussed with a view to educate students on the various skills that one can specialize in, such as IP design, IP integration, Verification, Synthesis, Physical Design, timing analysis, design for test, test development, post-silicon debug and validation. The tutorial be suitable for students who are interested in the field of semiconductors. It will also be useful to faculty who teach courses related to VLSI design. After attending the tutorial, the participant should have a feel for the industrial practices in VLSI Design. Q&A is highly encouraged.

    Dr.C.P.Ravikumar (Texas Instruments India)About the speaker: C.P. Ravikumar is presently the Director of Technical Talent Development at Texas Instruments, India. He leads the TI India Technical University which provides learning opportunities to employees of TI India. His earlier roles in TI include Director of University Relations and Senior Technologist (VLSI Test).  He is also an adjunct faculty at IIT Madras.  Before joining TI India in 2001, Ravikumar was a Professor of Electrical Engineering at the Indian Institute of Technology, Delhi (1991-2001). He also held a visiting position at the University of Southern California (1995-1996) and the position of Vice President (Training) atControlnet India Pvt Ltd (2000-2001).  He obtained his Ph.D. (Computer Engineering) from the University of Southern California (1991), M.E. in Computer Science with highest scores from Indian Institute of Science (1987) and B.E. in Electronics with a Gold Medal from Bangalore University (1983).
    He has published over 200 papers in leading International conferences and journals. He founded the VLSI Design and Test Symposium (VDAT) and was the General Chair of this event for 15 years, from its inception in 1998 to 2011. He is the author/editor/coauthor of over 12 books in areas of VLSI and has contributed several book chapters.  He is the editor of the Journal of VLSI and Electronic System Design and on the editorial board of the Journal of Electronic Testing – Theory and Applications and the Journal of Low Power Electronics. He has won the best paper award at IEEE International Conference on VLSI Design (2002) and VLSI Test Symposium (2005). He is a Senior Member of IEEE, honorary secretary of IEEE CAS Bangalore chapter (2004-current) which he founded, and the honorary secretary of VLSI Society of India (2003-2011).


    February
    Two Seminars on 20 February 2018 with common registration form.
    1: Seminar on Accurate Cell Characterization in the era of Variability
    Date: 20 February 2018
    Venue: TI India, Bangalore Campus, Bagmane Techpark, CV Raman Nagar
    Organized by: PragaTI (TI India Technical University) in association with IEEE CAS Bangalore Chapter and IEEE Bangalore Section
    Speaker: Bulusu Anand (Dept of ECE, IIT Roorkee)
    Time: 10.30 AM to 11.30 AM

    Abstract: Due to technology scaling and the consequent performance variability, VLSI circuits design methodologies need to consider device level phenomena/effects at a higher level of abstraction. The drive for a near threshold voltage operation creates an additional requirement of predicting the possibility of soft errors during the circuit/layout design phase, especially for storage elements. To address these issues, device-circuit linkages, which can be used in circuit/layout design and in standard cell characterization are very useful. We develop models which link device parameters to circuit level performance of inverters, buffers, inverter followed by transmission gate, multiplexers and important latches/flip-flops. We develop physics-based logic gate/latch delay/timing and soft error models in terms of device threshold voltage, carrier mobilities, and supply voltage. We then use these models to develop circuit/layout design methodologies in nominal/near-threshold voltage domains and also to improve standard cell characterization methodologies. In these methodologies we consider systematic variations due to layout dependent effects (LDEs), changes in supply voltage and temperature. We develop these methods for planar CMOS and multi-gate technologies.

    Bulusu Anand, IIT RoorkeeAbout the speaker: Bulusu Anand received the Ph.D. degree from the Indian Institute of Technology (IIT) Bombay, Mumbai, India, in December 2006. His doctoral work was on DTMOS device-circuit co-design. His research interest is in the areas of device physics, circuit-device interaction, and circuit performance models. After PhD, he worked in Freescale Semiconductor, India, wherein his work was in the domains of standard cells' sensitivity to process and device model variations. He is currently with the Department of Electronics and Communication Engineering, Indian Institute of Technology Roorkee, Roorkee, India.

    Registration: The seminar is open to all. There is no fee to attend, but prior registration is needed. Register at
    https://docs.google.com/forms/d/e/1FAIpQLSeDu_XNYDNh26ldPNR2Imj2dVCPyqn5bhXmGB6w7uhkDwBPPw/viewform?usp=sf_link
    no later than Feb 18. Your registration will be confirmed and further details will be mailed.


    2: Seminar on Recent Research in Semiconductor Area at IIT Roorkee
    Date: 20 February 2018
    Venue: TI India, Bangalore Campus, Bagmane Techpark, CV Raman Nagar
    Organized by: PragaTI (TI India Technical University) in association with IEEE CAS Bangalore Chapter and IEEE Bangalore Section
    Speaker: Sudeb Dasgupta (Dept of ECE, IIT Roorkee)
    Time: 11.30 AM to 12.30 PM

    Abstract: The talk will be mainly focussing on the research activities carried out in our group at IIT Roorkee. Primarily this will deal with device circuit co-design issues for devices such as bulk MOSFET, FinFETs, Tunnel FETs as well as reconfigurable FETs. We start with the device physics and extend it to extract the output characteristics followed by its circuit application in both Analog and Digital domain. We do a device level optimisation in order to achieve performance enhancement in various circuits such as memory etc. The talk will also discuss the low power design techniques used for the conventional SRAM cell. We will talk about the design and development of radiation hardened techniques for low earth orbiting satellites (LEOS).

    Sudeb DasguptaAbout the speaker: Sudeb Dasgupta, is presently working as an Associate Professor, in the Department of Electronics and Communication Engineering at Indian Institute of Technology, Roorkee. He received his PhD degree in Electronics Engineering from IIT-Banaras Hindu University, Varanasi in 2000. During his PhD work, he carried out research in the area of effects of ionizing radiation on MOSFET. He was member of faculty of Department of Electronics Engg.,at Indian School of Mines, Dhanbad (IIT-Dhanbad). In 2006, he joined as an Assistant Professor in the Department of Electronics and Communication Engineering at Indian Institute of Technology, Roorkee. He has authored/co-authored more than 250 research papers in peer reviewed international journals and conferences. He is a member of IEEE, EDS, ISTE and associate member of Institute of Nanotechnology, UK. He was awarded with Erasmus Mundus Fellowship of European Union in the year 2010 to work in the area of RDF at Politecnico Di Torino, Italy. He is the recipient of Indo-US Science and Technology Fellowship to work in the area of SRAM testing at University of Wisconsin at Madison, USA in the year 2011-12. He was also awarded with DAAD Fellowship to work on Analog Design using Reconfigurable Logic at TU, Dresden, Germany in the year 2013. He is also recipient of the prestigious Humboldt Fellowships at TU Berlin. His areas of interest are Nanoelectronics, Nanoscale MOSFET modeling and simulation, Design and Development of low power novel devices, FinFET based Memory Design, Emerging Devices in Analog Design and Design and development of reconfigurable logic. He has guided 15 Ph.D scholars. He is the coordinator of SMDP-C2S, a 100 cr multi-institutional project at IIT Roorkee.
    Currently he is supervising around 6 candidates leading to their Ph.D degree. He has been nominated for INAE Young Engineer Award. Dr. Dasgupta acted as a reviewer for IEEE Transactions on Electron Devices, IEEE Electron Device Letters, IEEE Transactions on Nanotechnology, Superlattice and Microstructures, International Journal of Electronics, Semiconductor Science and Technology, Nanotechnology, IEEE Transactions on VLSI Systems, Microelectronic Engineering, Microelectronic Reliability amongst other. He has also been member of technical committees of various international conferences.

    Registration: The seminar is open to all. There is no fee to attend, but prior registration is needed. Register at
    https://docs.google.com/forms/d/e/1FAIpQLSeDu_XNYDNh26ldPNR2Imj2dVCPyqn5bhXmGB6w7uhkDwBPPw/viewform?usp=sf_link
    no later than Feb 18. Your registration will be confirmed and further details will be mailed.


    ICAECC 2018 - Second International Conference on
    Advances in Electronics, Computers and Communications

    Organized by: REVA University, Bengaluru, India
    Technical Sponsors: IEEE Bangalore Section, IEEE ComSoc (IEEE Communications Society) Bangalore Section, IETE (Institute of Electronics and Telecommunication Engineering) and IEEE-CAS Society, Bangalore Chapter
    Theme: Fostering Information Technology Through Electronics, Computers and Communications
    Date: February 9-10, 2018
    Venue: School of ECE, REVA University, Rukmini Knowledge Park, Yelahanka, Bengaluru - 560064, India

    ICAECC 2018

    Download ICAECC 2018 - Conference Announcement (PDF)
    Visit the Conferece web site for more information.

    About the conference: The 2018 Second International Conference on Advances in Electronics, Computers and Communications (ICAECC 2018) will be held at REVA University, Bangalore, India. The conference presents an open forum for scientists, researchers and engineers to exchange the latest innovations and research advancements in the areas of next-generation electronics, computers, communication architectures, protocols and algorithms, content systems, applications and services. The conference will include plenary sessions and invited talks from eminent researchers on the state of the art in related areas. Contributions describing original research, surveys and applications are invited.

    Aims and Scope of the Conference: The Conference serves as a major international forum for presenting and sharing recent accomplishments and technological developments in the field of Advances in Electronics, Computers and Communications.

  • It Involves participants (researches, developers and users) from academics, industries and research laboratories coming together to discuss recent advances and trends.
  • Awards will be given to the best paper at the conference.
  • Conference content will be submitted for inclusion into IEEEXplore as well as other Abstracting and Indexing (A & I) databases
  • Important Dates:
    First Call of Paper21st September 2017
    Submission Deadline5th December 2017
    Notification of Acceptance of Papers15th January 2018
    Camera Ready Paper Submission25th - 30th January 2018
    Author Registration20th - 30th January 2018


    January
    Seminar on GaN Power Devices: Characteristics, Design Considerations and Applications
    Jointly organized by: IEEE PELS and IEEE CAS Bangalore Chapter
    Speaker: Salil Chellappan (Systems Manager – Power Delivery, Industrial Systems, Texas Instruments)
    Date: 18 January 2018
    Time: 3.00 PM - 4.00 PM
    Venue: IISc, Bangalore, Department of Electrical Engineering

    Registration: The seminar is open to all. There is no fee to attend, but prior registration is needed. Register at
    https://docs.google.com/forms/d/e/1FAIpQLSfaUkg8SlLs5ahsR8rnCTiLpkJXikB81uxFud175w8YovDpIg/viewform?usp=sf_link
    no later than 17 January 2018. Your registration will be confirmed and further details will be mailed.

    Abstract:
    In this presentation, the characteristics, design considerations and a typical application of GaN power devices will be discussed. The first half of the presentation will focus on the application related characteristics of GaN power devices. A comparative study of available device architectures (like enhancement and depletion mode), specifications and packaging vis-a-vis power conversion applications will be presented.
    The second half will focus more on a practical implementation using GaN devices – a "Zero Voltage Switched Interleaved Critical Conduction Mode Totem pole Bridgeless PFC", that extends the switching frequency range to the MHz region. The background, implementation aspects and results will be presented.

    Salil ChellappanAbout the speaker:
    Salil Chellappan, Systems Manager - Power Delivery, Industrial Systems, Texas Instruments
    Salil Chellappan in his present role drives the growth of TI's business in Power Delivery end equipment sector by executing strategic reference designs and other collateral for release on TI website. Prior to this role, Salil was Lead Engineer in Power Design Services where he was responsible for developing customer driven power designs for the growth of TI's business in India. He was elected to TI's technical ladder in 2012 for his contributions in the area of power conversion. Salil has more than 27 years' experience in power conversion and analog design that includes ten years in TI and the rest in various high profile organizations like GE, Power Integrations, Lucent Technologies and Bharat Electronics.
    He has a Bachelor's Degree in Electronics & Communication Engineering from Kerala University. He dedicates his spare time to urban farming and aquascaping.


    Two Seminars on 10 January 2018
    1. Seminar on BIST for High-Quality and Low-Cost Testing
    Organized by: IEEE CAS Bangalore Chapter, in cooperation with Texas Instruments (India) and IEEE Bangalore Section
    Speaker: Sule Ozev (Asc.Prof, Arizona State University)
    Date: 10 January 2018
    Time: 10AM - 11AM
    Venue: TI India Bangalore Campus, Bagmane Tech Park, CV Raman Nagar, Bangalore 93

    Registration: The seminar is open to IEEE members. There is no fee to attend, but prior registration is needed. Register at
    https://docs.google.com/forms/d/e/1FAIpQLSdetGJnjUYlp2efc-38P3m-wi3v0Ud2Yc2RQXTgYKx4YKbHmw/viewform?usp=sf_link no later than Jan 8. Your registration will be confirmed and further details will be mailed./p>

    Abstract: Built-in self-test (BIST) can potentially reduce the overall cost of production test and calibration by allowing access to embedded components at low cost. In this talk, an overview for analog/RF BIST will be presented along with an emphasis on BIST approaches for static and dynamic testing of power converters. For static test, a small footprint zoom-ADC is presented. For dynamic test, transfer function characterization through PRBS stimulation will be presented. Measurement results will be discussed.

    About the speaker: Sule Ozev received her bachelor's degree in electrical engineering from Bogazici University, Turkey, and her master's and doctoral degrees in computer science and engineering from University of California, San Diego in 1995, 1998 and 2002, respectively. Ozev joined the electrical engineering faculty in August 2008 and is currently an associate professor. She served as an associate editor for IEEE Transactions on VLSI systems (2007-2014) and serves on various program committees, including IEEE VLSI Test Symposium (2008-2015), IEEE International Test Conference (2007-2015), IEEE International Conference on Computer Design (2004-2015), and IEEE European Test Symposium (2006-2015). She is the program chair of the International Conference on Computer Design (2013-2015) and was the general chair for IEEE International Mixed-Signals, Sensors and Systems 2009. In 2006, Ozev received an NSF CAREER Award. She has published over 100 conference and journal papers and holds one U.S. patent.
    Research expertise
    Self-test and self-calibration for wireless transceivers, analysis and mitigation of process variations for mixed signal and digital circuits, fault-tolerant and reconfigurable heterogeneous systems, mixed signal circuit testing.

     

    2. Seminar on Assertions for Analog and Mixed-Signal Verification
    Organized by: IEEE CAS Bangalore Chapter, in cooperation with Texas Instruments (India) and IEEE Bangalore Section
    Speaker: Dr Pallab Dasgupta (Dept of CSE, IIT Kharagpur)
    Date: January 10, 2018
    Time: 11.15AM - 12.15PM
    Venue: Texas Instruments India, Bangalore Campus (Remote participation is possible)

    Registration: The seminar is open to IEEE members. There is no fee to attend the seminar. However, you must register at the following link:
    https://docs.google.com/forms/d/e/1FAIpQLSd6kwL7DA8nLxiEc47LQPbm9tWs9kXYCVFKqrd72_MfgnhMHQ/viewform?usp=sf_link before January 8, 2018.
    Confirmations and further directions will be sent to those registered opting to attend in person or remotely through webex through e-mail.

    Abstract: Assertions have transformed the landscape of verification technology, leading to nearly ubiquitous adoption of industry standards such as SystemVerilog Assertions (SVA) and Property Specification Language (PSL). In view of the increasing volume of analog components in mixed-signal SOCs, there is a growing need for enabling assertion based verification of AMS circuits. This talk outlines the emerging nuances of AMS assertions, focusing on a wide variety of questions. Are AMS assertions semantically different from their digital counterparts? Do we need fundamentally different CAD algorithms for checking AMS assertions? Does AMS assertion checking adversely affect the analog simulator's performance? Can AMS assertions be used for coverage analysis? Are AMS assertions rich enough to express most things that an AMS designer intends to validate?

    Dr.Pallab DasguptaAbout the speaker: Dr Pallab Dasgupta is a professor with the department of Computer Science and Engineering at IIT Kharagpur, which gives him the license to teach some of the great young minds of India, collaborate with many companies who come to him with very tough problems, and provide research guidance to some students who are reasonably determined to get their PhD degrees. As the current Dean of Sponsored Research and Industrial Consultancy of the largest IIT, he tries to comprehend the delightfully diverse areas of competence of his colleagues and facilitate their connections with various R&D opportunities. As a personal level, he plays, though not very well, an Indian instrument called sitar. Other not so relevant information about him can be found in his website: http://cse.iitkgp.ac.in/~pallab

    About the Speaker's Research Group: The Formal Methods Research Group, IIT Kharagpur works on a wide variety of application domains, including verification of digital and analog integrated circuits, verification of real time control systems, software verification, verification of smart electrical grids and verification of railway signalling and train control systems. The group develops tools and technology for formal verification and applies them to real world problems in collaboration with a wide spectrum of industries including Intel, IBM, Synopsys, General Motors, SRC, Indian Railways, Hindustan Aeronautics Ltd., and Freescale Semiconductors.


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