Events - 2018
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Hands-on Introduction to Digital Design and Verification through Verilog and System Verilog
Organizers: Jointly Organized by IEEE Student Branch KLEIT and IEEE CAS Bangalore Chapter
Speaker: Dr. C.P. Ravikumar (Texas Instruments India)
Date: 25 November 2018 (Sunday)
Time: 9.00am - 4.00pm (Registration: 8.30am)
Venue: Ekalaksya Lab, Dept. of ECE, K.L.E Institute of Technology, Hubbali-30, Karnataka
Registration: Open to all student IEEE members & faculty from engineering colleges. At most 30 participants will be permitted. Please register online at: https://goo.gl/forms/oOi4L6mLZan1qMz73 no later than 20 November 2018. Your registration will be confirmed and further details will be mailed.
IEEE student/Professional members: Rs.350/-
Non-IEEE members: Rs.500/-
Registration fee is to be paid to: KLEIT IEEE Student Branch (Chq/DD or NEFT)
Bank Name: Syndicate Bank
Account No: 12432010019851
IFSC Code: SYNB0001243
Alternatively, download the PDF Registration Form and send it filled to firstname.lastname@example.org
Abstract: Functional Verification is one of the most effort-intensive steps in VLSI design. The participants of this workshop will get an introduction to the topic of digital design verification. In particular, Verilog and System Verilog will be discussed and RTL coding and development of test benches will be provided.
About the speaker: Presently the Director of Technical Talent Development at Texas Instruments, India. He leads the TI India Technical University which provides learning opportunities to employees of TI India. His earlier roles in TI include Director of University Relations and Senior Technologist (VLSI Test). He is also an adjunct faculty at IIT Madras. Before joining TI India in 2001, He was a Professor of Electrical Engineering at the IIT, Delhi (1991-2001). He also held a visiting position at the University of Southern California (1995-1996) and was Vice President (Training) at Controlnet India Pvt Ltd (2000-2001).