IEEE - CAS Bangalore Chapter, India     CAS Chapter - Region 10
Institute of Electrical and Electronics Engineers - Circuits and Systems Society
Goals: To conduct seminars, workshops, and other events pertaining to all aspects of electronic circuits and systems

Events - 2018
All external links open in a New Tab/Window
Hands-on Introduction to Digital Design and Verification through Verilog and System Verilog
Organizers: Jointly Organized by IEEE Student Branch KLEIT and IEEE CAS Bangalore Chapter


Speaker: Dr. C.P. Ravikumar (Texas Instruments India)
Date: 25 November 2018 (Sunday)
Time: 9.00am - 4.00pm (Registration: 8.30am)
Venue: Ekalaksya Lab, Dept. of ECE, K.L.E Institute of Technology, Hubbali-30, Karnataka

Registration: Open to all student IEEE members & faculty from engineering colleges. At most 30 participants will be permitted. Please register online at: no later than 20 November 2018. Your registration will be confirmed and further details will be mailed.

Registration fee: The fee (incl. tax) includes lunch and refreshment.

IEEE student/Professional members: Rs.350/-
Non-IEEE members: Rs.500/-

Registration fee is to be paid to: KLEIT IEEE Student Branch (Chq/DD or NEFT)
Bank Name: Syndicate Bank
Account No: 12432010019851
IFSC Code: SYNB0001243

Alternatively, download the PDF Registration Form and send it filled to

Abstract: Functional Verification is one of the most effort-intensive steps in VLSI design. The participants of this workshop will get an introduction to the topic of digital design verification. In particular, Verilog and System Verilog will be discussed and RTL coding and development of test benches will be provided.

Pre-requisites: The participant must have taken a class on Digital Design. Prior exposure to VLSI Design and VHDL or Verilog will be useful.

Infrastructure: Participants are expected to bring their laptop and charger to the class. Confirmed participants will be provided additional instructions on software installation required for the course.

Dr. C.P. RavikumarAbout the speaker: Presently the Director of Technical Talent Development at Texas Instruments, India. He leads the TI India Technical University which provides learning opportunities to employees of TI India. His earlier roles in TI include Director of University Relations and Senior Technologist (VLSI Test). He is also an adjunct faculty at IIT Madras. Before joining TI India in 2001, He was a Professor of Electrical Engineering at the IIT, Delhi (1991-2001). He also held a visiting position at the University of Southern California (1995-1996) and was Vice President (Training) at Controlnet India Pvt Ltd (2000-2001).

He obtained his Ph.D. (Computer Engineering) from the University of Southern California (1991), M.E. in Computer Science with highest scores from Indian Institute of Science (1987) and B.E. in Electronics with a Gold Medal from Bangalore University (1983). He has published over 200 papers in leading International conferences and journals. He founded the VLSI Design and Test Symposium (VDAT) and was the General Chair of this event for 15 years, from its inception in 1998 to 2011. He is the author/editor/coauthor of over 12 books in areas of VLSI and has contributed several book chapters.

He is the editor of the Journal of VLSI and Electronic System Design and on the editorial board of the Journal of Electronic Testing Theory and Applications and the Journal of Low Power Electronics. He has won the best paper award at IEEE International Conference on VLSI Design (2002) and VLSI Test Symposium (2005). He is a Senior Member of IEEE, honorary secretary of IEEE CAS Bangalore chapter (2004-current) which he founded, and the honorary secretary of VLSI Society of India (2003-2011).