IEEE - CAS Bangalore Chapter, India     CAS Chapter - Region 10
Institute of Electrical and Electronics Engineers - Circuits and Systems Society
Goals: To conduct seminars, workshops, and other events pertaining to all aspects of electronic circuits and systems
Event Reports - 2018
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March
Hands-on Introduction to Design and Verification through Verilog and System Verilog
24 March 2018
Texas Instruments India, Bangalore Campus, Bagmane Techpark, CV Raman Nagar
Report by C.P.Ravikumar ... Photos

verilog-mar18 A Hands-on Introduction entitled Design and Verification through Verilog and System Verilog was organized by IEEE CAS Bangalore Chapter with support by Texas Instruments, India and IEEE Bangalore Section on 24 March 2018 at Texas Instruments India, Bangalore Campus, Bagmane Techpark, CV Raman Nagar.

Dr. C.P. Ravikumar of Texas Instruments India was the instructor for the one-day program that was targeted at students and faculty with prior knowledge on Digital Design and were required to be familiar with combinational and sequential logic design. Prior exposure to VLSI Design and VHDL or Verilog were also mentioned to be a requirement to understand the advanced topics. The tutorial began wth an introduction to the topic of digital design verification. Verilog and System Verilog were discussed and provided examples of RTL coding and development of testbenches.

The participants were excited to learn about VLSI design, Verilog, System Verilog and industrial design practices. The tutorial was hands-on, with simulation exercises. The participants made use of public-domain tools. Starting from a simple combinational logic design, several concepts of Verilog HDL were unfolded. The basic example was refined successively to illustrate further concepts. The next exercise was about synchronous sequential logic design. It started with an example that was small and grew it to include more advanced concepts.The example of a built-in self-test system was looked into. Finally, the tutorial focused on System-Verilog, the motivation for SV, and the new language constructs that SV includes to simplify the task of a verification engineer.

IEEE Bangalore Section supported the event, with Mr.Suraj helping in publicizing the event. Divya M (member of Execom, IEEE Bangalore Section) explained the benefits of membership to the participants during the valedictory function.

The audience was a mix of students, teachers from engineering colleges, and a few professionals. About 30% of the 28 participants were members of IEEE. There was an online test that the participants took at the end of the tutorial. The average score was 78%. The top three scorers also received prizes! There was a positive feedback with expectations of a similar workshop with longer duration exclusively for research scholars. Many opined on getting an insight into industrial practices that take place in the semiconductor industry, and on having obtained a lot more than expected from the program.

A summation of this event by the instructor on IEEE Blog entitled A full-day tutorial on VLSI Design Verification is available.

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Panel Discussion during Cyberia'18 (26 February to 4 March 2018)
Topic: How to effectively embed skill development into Educational Program so that the graduates are rendered industry ready?
3 March 2018
SJCE, Mysuru
Report by C.P.Ravikumar ... Photos

cyberia18-sjce A Panel Discusssion entitled How to effectively embed skill development into Educational Program so that the graduates are rendered industry ready? was conducted on 3 March 2018 as a part of Cyberia'18 an IEEE Student conference (26 February to 4 March 2018). The event was organized by IEEE-SJCE, Mysuru at Sri Jayachamarajendra College of Engineering, Mysuru - 570 006.

The panel was moderated by B. Ramkumar (former Tektronix) and the panelists included Varun Shastri, Working at Applied Materials, Dr. Narasimha Kaulgad, Professor NIE, Mysuru, Dr. Bindu Thomas, Professor VVIET, Arun Pradeep, CEO of Neutrinos Solutions, Ramesh Agrahar, Vice President Kaynes, Srikantaswamy Bisilavaadi, Robert Bosch, and C.P. Ravikumar, Director of Technical talent development, TI India.

ieee-sjce"How to effectively embed skill development into Educational Program so that the graduates are rendered industry ready?" This was the topic of a panel discussion organized at the inauguration of Cyberia 2018, an annual student technical festival organized by SJCE Mysuru. I had the privilege to be the Chief Guest at the inauguration as well as a panelist. My thanks are due to Prof. Sudharshan Patil, faculty counsellor of the IEEE SJCE branch, for this invitation. I understand that this is the second time I have had this honor. Several years ago, Prof. C.R. Venugopal, who was then the branch counsellor of the branch, had extended a similar invitation to me.

This year, my co-panelists were Mr. Srikantaswamy Bisilavaadi from Robert  Bosch, Mr.Ramesh Agrahar, Vice President of Kaynes, Mr. Arun Pradeep, CEO of Neutrinos Solutions, Dr. Narasimha Kaulgad, Professor NIE, Mysuru, Dr. Bindu Thomas, Professor  at VVIET, Mysuru, and Varun Shastri ,employee of Applied Materials. The panel was moderated by B. Ramkumar (former Tektronix). Several faculty members of SJCE as well as students attended the panel discussion and raised interesting questions.

Let me summarize some of the important points that came up during discussion. I want to emphasize that in a panel discussion, there are no conclusions. It is a discussion where ideas are tossed across to make people think.

  • Project-based learning
  • Some of the panelists from the industry felt that students must focus on "project-based learning." In today’s competitive world, industry is looking for students who have the ability to solve practical problems and have a higher level of awareness of the trends. One panelist made the following remark. "When I interview candidates, I ask them what they can do. Unfortunately, I am unable to get a clear answer. Professionals such as carpenters or chefs will be able to give a clear answer to such a question, but engineers are unable to do so." This is food for thought for everyone. Should engineers have a specific answer for such a question? Are they expected to do one thing and only one thing when they graduate? What is the aim of engineering education?

  • Softskills
  • Some panelists felt that it is important for students to pick up soft skills such as good communication skills. Both written and oral communication skills are important for an engineer. Be warned, however, that softskills are necessary but not sufficient to land a job. Remember, you will have to do well on exams to be shortlisted, get good scores on written tests and excel in technical interviews.

  • Role of Industry and Academia
  • There was a discussion on what industry’s role is in this process. Of course, industry professionals can provide inputs to the committees that design curricula. Companies typically invest in one or more colleges from where they tend to recruit. They may send engineers to teach courses. They may provide internship opportunities to students. They may provide free licenses to software or free IC samples, etc. During the Q&A, there was a discussion on whether the viewpoints of students must be given consideration in framing the curriculum. There was a also discussion on what academia can do towards imparting skills. In this connection, there was a discussion on upgrading the curricula. It was mentioned that VTU is planning to reduce the number of course credits in undergraduate programs, which would reduce the burden of classes and allow students to focus on project-based learning.

    The panel discussion was lively and generated good interest among the participants. Of course, as is always the case, a panel discussion generates more questions than answers. I have had the privilege to attend, moderate, organize, and participate in several panel discussions at IEEE conferences such as VDAT, VLSI Design Conference, VTS, and ITC to name a few. I congratulate the organizing committee of Cyberia-2017 for having organized yet another interesting panel discussion.

    A number of faculty and students from Mysuru were present at the inauguration of Cyberia-2018.

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    Tutorial entitled Introduction to VLSI Design - An Industry Perspective
    3 March 2018
    GSSS Institute Of Engineering And Technology For Women, Mysore
    Report by C.P.Ravikumar ... Photos

    vlsi-mar18 The Departments of Telecom and Electronics & Communication at the GSSS Institute of Technology for Women, Mysuru, organized a tutorial on Introduction to VLSI Design - An Industry Perspective in cooperation with IEEE CAS Bangalore Chapter. The tutorial was delivered by Dr C.P. Ravikumar of Texas Instruments.

    The event began with a brief inaugural ceremony where Dr. Parameshachari, Head of the Department of Telecom, Dr. Satyanarayana, Head of the Department of E&C, and Dr. M.K. Shivakumar, Principal of GSSITW were present. The tutorial was attended by the third-year undergraduate students of Telecommunication and Electronics-& Communication. About 200 students were present in the audience. In addition, several faculty members attended the event. A special guest included Dr Sukumar, a senior professor, former Head of the Department of Biomedical Engineering at SJCE, Mysuru.

    Dr Ravikumar had planned the tutorial as a "quiz" to keep the audience engaged. He asked a series of questions to the audience on a range of topics related to SoC design and design flow. There were even prizes for those who participated in the discussion. Prof. Parameshachari offered the vote of thanks.

    I N D E X   T O P February
    Two Seminars were held on 20 February 2018 with the speakers from IIT Roorkee serving as senior faculty members.
    1. Seminar entitled Accurate Cell Characterization in the era of Variability
    20 February 2018 (10.30 AM to 11.30 AM)
    TI India, Bangalore Campus, Bagmane Techpark, CV Raman Nagar
    Report by C.P.Ravikumar ... Photos

    cellchar-feb18 A Seminar entitled Accurate Cell Characterization in the era of Variability was organized by PragaTI (TI India Technical University) in association with IEEE CAS Bangalore Chapter and IEEE Bangalore Section on 20 February 2018 (10.30 AM to 11.30 AM) at TI India, Bangalore Campus, Bagmane Techpark, CV Raman Nagar.

    Bulusu Anand of (Dept of ECE, IIT Roorkee) was the invited speaker. The talk began with the need for VLSI circuits design methodologies to consider device level phenomena/effects at a higher level of abstraction owing to technology scaling and the consequent performance variability. Especially since the drive for a near threshold voltage operation creates an additional requirement of predicting the possibility of soft errors during the circuit/layout design phase, particularly for storage elements. The speaker noted that to address these issues, device-circuit linkages, which can be used in circuit/layout design and in standard cell characterization are very useful.

    He spoke about IIT Roorkee developing models which link device parameters to circuit level performance of inverters, buffers, inverter followed by transmission gate, multiplexers and important latches/flip-flops. And also about the institute developing physics-based logic gate/latch delay/timing and soft error models in terms of device threshold voltage, carrier mobilities, and supply voltage. He explained how they then use these models to develop circuit/layout design methodologies in nominal/near-threshold voltage domains and also to improve standard cell characterization methodologies. In these methodologies we consider systematic variations due to layout dependent effects (LDEs), changes in supply voltage and temperature. The team as he explained develops these methods for planar CMOS and multi-gate technologies.

    We had around 16 participants including some IEEE members. The event was also available as a webinar via the TI WebEx portal and was attended by 5 participants remotely.

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    2. Seminar entitled Recent Research in Semiconductor Area at IIT Roorkee
    20 February 2018 (11.30 AM to 12.00 PM)
    TI India, Bangalore Campus, Bagmane Techpark, CV Raman Nagar
    Report by C.P.Ravikumar ... Photos

    iitr-feb18 A Seminar entitled Recent Research in Semiconductor Area at IIT Roorkee was organized by PragaTI (TI India Technical University) in association with IEEE CAS Bangalore Chapter and IEEE Bangalore Section on 20 February 2018 (11.30 AM to 12.00 PM) at TI India, Bangalore Campus, Bagmane Techpark, CV Raman Nagar.

    Sudeb Dasgupta of (Dept of ECE, IIT Roorkee) was the invited speaker. His talk focused on the research activities carried out by their group at IIT Roorkee. Primarily it dealt with device circuit co-design issues for devices such as bulk MOSFET, FinFETs, Tunnel FETs as well as reconfigurable FETs. He explained on how they start with the device physics and extend it to extract the output characteristics followed by its circuit application in both Analog and Digital domain. The team does a device-level optimisation in order to achieve performance enhancement in various circuits such as memory etc.

    The speaker also discussed the low power design techniques used for the conventional SRAM cell, and about the design and development of radiation hardened techniques for low earth orbiting satellites (LEOS).

    We had around 16 participants including some IEEE members. The event was also available as a webinar via the TI WebEx portal and was attended by 5 participants remotely.

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    January
    Seminar entitled GaN Power Devices: Characteristics, Design Considerations and Applications
    18 January 2018
    IISc, Bangalore, Department of Electrical Engineering
    Report by C.P.Ravikumar ... Photos

    gan-jan18 A Seminar entitled GaN Power Devices: Characteristics, Design Considerations and Applications was jointly organized by IEEE PELS (Power Electronics Society) and IEEE CAS, Bangalore Chapter on 18 January 2018 at IISc, Bangalore, Department of Electrical Engineering.

    Salil Chellappan (Systems Manager – Power Delivery, Industrial Systems) of Texas Instruments was the invited speaker. The presentation covered the characteristics, design considerations and a typical application of GaN power devices in two parts. The first half focused on the application related characteristics of GaN power devices. A comparative study of available device architectures (like enhancement and depletion mode), specifications and packaging vis-a-vis power conversion applications were presented.

    The second half focused more on a practical implementation using GaN devices – a "Zero Voltage Switched Interleaved Critical Conduction Mode Totem pole Bridgeless PFC", that extends the switching frequency range to the MHz region. The background, implementation aspects and results were also presented.

    We had around 36 participants including some IEEE members.

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    IEEE-CAS Society Bangalore Chapter had arranged two seminars back-to-back on 10 January 2018.

    1. Seminar entitled BIST for High-Quality and Low-Cost Testing
    10 January 2018 (10 to 11 AM)
    Texas Instruments India, Bangalore Campus
    Report by C.P.Ravikumar ... Photos

    bist-jan18 A Seminar entitled BIST for High-Quality and Low-Cost Testing was organized by IEEE CAS Bangalore Chapter, in cooperation with Texas Instruments and IEEE Bangalore Section on 10 January 2018 at Texas Instruments India, Bangalore Campus.

    Sule Ozev, an Associate Professor at Arizona State University was the invited speaker. She highlighted the main aspect of the topic, on Built-in self-test (BIST) potentially reducing the overall cost of production test and calibration by allowing access to embedded components at low cost. She presented an overview for analog/RF BIST along with an emphasis on BIST approaches for static and dynamic testing of power converters. For static test, a small footprint zoom-ADC was presented, and for dynamic test, transfer function characterization through PRBS stimulation was covered. The measurement results in both were discussed.

    We had around 20 participants including some IEEE members. The event was also available as a webinar via the TI WebEx portal and was attended by 15 participants remotely.

    2. Seminar entitled Assertions for Analog and Mixed-Signal Verification
    10 January 2018 (11.15 to 12.15 PM)
    Texas Instruments India, Bangalore Campus
    Report by C.P.Ravikumar ... Photos

    analog-msv-jan18 A Seminar entitled Assertions for Analog and Mixed-Signal Verification was organized by IEEE CAS Bangalore Chapter, in cooperation with Texas Instruments (India) and IEEE Bangalore Section on 10 January 2018 at Texas Instruments India, Bangalore Campus.

    Dr.Pallab Dasgupta of the Dept of CSE, IIT Kharagpur was the invited speaker. He pointed about Assertions having transformed the landscape of verification technology, leading to nearly ubiquitous adoption of industry standards such as SystemVerilog Assertions (SVA) and Property Specification Language (PSL). And in view of the increasing volume of analog components in mixed-signal SOCs, he felt there is a growing need for enabling assertion based verification of AMS circuits. The talk outlined the emerging nuances of AMS assertions, focusing on a wide variety of questions. He raised the questions on if AMS assertions are semantically different from their digital counterparts, and if we need fundamentally different CAD algorithms for checking AMS assertions? The other pointers were if AMS assertion checking adversely affect the analog simulator's performance, and if AMS assertions can be used for coverage analysis? He also queried if AMS assertions are rich enough to express most things that an AMS designer intends to validate.

    We had around 20 participants including some IEEE members. The event was also available as a webinar via the TI WebEx portal and was attended by 20 participants remotely.

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