IEEE - CAS Bangalore Chapter, India     CAS Chapter - Region 10
Institute of Electrical and Electronics Engineers - Circuits and Systems Society
Goals: To conduct seminars, workshops, and other events pertaining to all aspects of electronic circuits and systems
Event Reports - 2018
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January
Seminar entitled GaN Power Devices: Characteristics, Design Considerations and Applications
18 January 2018
IISc, Bangalore, Department of Electrical Engineering
Report by C.P.Ravikumar ... Photos

gan-jan18 A Seminar entitled GaN Power Devices: Characteristics, Design Considerations and Applications was jointly organized by IEEE PELS (Power Electronics Society) and IEEE CAS, Bangalore Chapter on 18 January 2018 at IISc, Bangalore, Department of Electrical Engineering.

Salil Chellappan (Systems Manager Power Delivery, Industrial Systems) of Texas Instruments was the invited speaker. The presentation covered the characteristics, design considerations and a typical application of GaN power devices in two parts. The first half focused on the application related characteristics of GaN power devices. A comparative study of available device architectures (like enhancement and depletion mode), specifications and packaging vis-a-vis power conversion applications were presented.

The second half focused more on a practical implementation using GaN devices a "Zero Voltage Switched Interleaved Critical Conduction Mode Totem pole Bridgeless PFC", that extends the switching frequency range to the MHz region. The background, implementation aspects and results were also presented.

We had around 36 participants including some IEEE members.

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IEEE-CAS Society Bangalore Chapter had arranged two seminars back-to-back on 10 January 2018.

1. Seminar entitled BIST for High-Quality and Low-Cost Testing
10 January 2018 (10 to 11 AM)
Texas Instruments India, Bangalore Campus
Report by C.P.Ravikumar ... Photos

bist-jan18 A Seminar entitled BIST for High-Quality and Low-Cost Testing was organized by IEEE CAS Bangalore Chapter, in cooperation with Texas Instruments and IEEE Bangalore Section on 10 January 2018 at Texas Instruments India, Bangalore Campus.

Sule Ozev, an Associate Professor at Arizona State University was the invited speaker. She highlighted the main aspect of the topic, on Built-in self-test (BIST) potentially reducing the overall cost of production test and calibration by allowing access to embedded components at low cost. She presented an overview for analog/RF BIST along with an emphasis on BIST approaches for static and dynamic testing of power converters. For static test, a small footprint zoom-ADC was presented, and for dynamic test, transfer function characterization through PRBS stimulation was covered. The measurement results in both were discussed.

We had around 20 participants including some IEEE members. The event was also available as a webinar via the TI WebEx portal and was attended by 15 participants remotely.

2. Seminar entitled Assertions for Analog and Mixed-Signal Verification
10 January 2018 (11.15 to 12.15 PM)
Texas Instruments India, Bangalore Campus
Report by C.P.Ravikumar ... Photos

analog-msv-jan18 A Seminar entitled Assertions for Analog and Mixed-Signal Verification was organized by IEEE CAS Bangalore Chapter, in cooperation with Texas Instruments (India) and IEEE Bangalore Section on 10 January 2018 at Texas Instruments India, Bangalore Campus.

Dr.Pallab Dasgupta of the Dept of CSE, IIT Kharagpur was the invited speaker. He pointed about Assertions having transformed the landscape of verification technology, leading to nearly ubiquitous adoption of industry standards such as SystemVerilog Assertions (SVA) and Property Specification Language (PSL). And in view of the increasing volume of analog components in mixed-signal SOCs, he felt there is a growing need for enabling assertion based verification of AMS circuits. The talk outlined the emerging nuances of AMS assertions, focusing on a wide variety of questions. He raised the questions on if AMS assertions are semantically different from their digital counterparts, and if we need fundamentally different CAD algorithms for checking AMS assertions? The other pointers were if AMS assertion checking adversely affect the analog simulator's performance, and if AMS assertions can be used for coverage analysis? He also queried if AMS assertions are rich enough to express most things that an AMS designer intends to validate.

We had around 20 participants including some IEEE members. The event was also available as a webinar via the TI WebEx portal and was attended by 20 participants remotely.

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